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    SRAM with buffered-read bit cells and its testing
    1.
    发明授权
    SRAM with buffered-read bit cells and its testing 有权
    具有缓冲读取位单元的SRAM及其测试

    公开(公告)号：US09472268B2

    公开(公告)日：2016-10-18

    申请号：US13135198

    申请日：2011-06-27

    申请人： Xiaowei Deng ,  Wah Kit Loh

    发明人： Xiaowei Deng ,  Wah Kit Loh

    IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C8/16 ,  G11C29/02 ,  G11C11/41

    CPC分类号： G11C11/419 ,  G11C8/16 ,  G11C11/41 ,  G11C29/022

    摘要： An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200,202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

    摘要翻译： 公开了具有缓冲读位元的SRAM（图1-6）。 集成电路包括多个存储单元（102）。 每个存储单元具有多个晶体管（200,202）。 第一存储器单元（图2）被布置为响应于有效写入字线（WWL）存储数据信号，并且响应于有源读取字线（RWL）产生数据信号。 形成在集成电路上的测试电路（104）可操作以测试第一存储单元的多个晶体管中每个晶体管的电流和电压特性（图7-10）。

    Efficient static random-access memory layout
    2.
    发明授权
    Efficient static random-access memory layout 有权
    高效的静态随机存取存储器布局

    公开(公告)号：US08760927B2

    公开(公告)日：2014-06-24

    申请号：US13558003

    申请日：2012-07-25

    申请人： Xiaowei Deng

    发明人： Xiaowei Deng

    IPC分类号： G11C11/34

    CPC分类号： H01L27/0207 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116

    摘要： A complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with no well contacts within the memory array. Modern sub-micron CMOS structures have been observed to have reduced vulnerability to latchup. Chip area is reduced by providing no well contacts within the array. Wells of either or both conductivity types may electrically float during operation of the memory. In other implementations, extensions of the array wells into peripheral circuitry may be provided, with well contacts provided in those extended portions.

    摘要翻译： 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM），在存储器阵列内没有良好的接触。 已经观察到现代的亚微米CMOS结构已经减少了闭锁的脆弱性。 通过在阵列内没有提供良好的接触来减小芯片面积。 导电类型中的一种或两种的阱可在存储器的操作期间电浮动。 在其他实施方案中，可以提供阵列阱到外围电路的扩展，其中提供在这些延伸部分中的阱触点。

    Disturb-free static random access memory cell
    3.
    发明授权
    Disturb-free static random access memory cell 有权
    无噪音静态随机存取存储单元

    公开(公告)号：US08654575B2

    公开(公告)日：2014-02-18

    申请号：US13149489

    申请日：2011-05-31

    申请人： Xiaowei Deng

    发明人： Xiaowei Deng

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412

    摘要： A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column.

    摘要翻译： 固态存储器，其中每个存储器单元包括交叉点可寻址写入元件。 每个存储单元包括诸如一对交叉耦合的反相器的存储元件和用于将存储节点中的一个耦合到用于包含单元的列的读位线的读缓冲器。 每个存储单元的写元件包括由包含单元的行的写字线控制的一对或一对写选择晶体管，以及连接到相应存储节点并与写选择晶体管串联连接的写通晶体管。 写通道晶体管由包含单元的列的写位线选通。 在操作中，取决于由该列的互补写位线承载的数据状态，写参考被耦合到所选列和所选行中的存储单元的存储节点之一。

    Static random access memory cell with single-sided buffer and asymmetric construction
    4.
    发明授权
    Static random access memory cell with single-sided buffer and asymmetric construction 有权
    静态随机存取存储单元采用单面缓冲和非对称构造

    公开(公告)号：US08654562B2

    公开(公告)日：2014-02-18

    申请号：US13477901

    申请日：2012-05-22

    申请人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

    发明人： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshadri ,  Zhonghai Shi

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C11/412 ,  H01L27/1104

    摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

    摘要翻译： 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

    Solid-state memory cell with improved read stability
    5.
    发明授权
    Solid-state memory cell with improved read stability 有权
    固态存储单元具有改善的读取稳定性

    公开(公告)号：US08498143B2

    公开(公告)日：2013-07-30

    申请号：US13104735

    申请日：2011-05-10

    申请人： Xiaowei Deng

    发明人： Xiaowei Deng

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： A solid-state memory in which stability assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an isolation gate connected between one of the storage nodes and the input of the opposite inverter. The isolation gate may be realized by complementary MOS transistors connected in parallel, and receiving complementary isolation control signals. In read cycles, or in unselected columns during write cycles, the isolation gate is turned off slightly before the word line is energized, and turned on at or after the word line is de-energized. By isolating the input of one inverted from the opposite storage node, the feedback loop of the cross-coupled inverters is broken, reducing the likelihood of a cell stability failure.

    摘要翻译： 其中在每个存储单元内实现稳定性辅助电路的固态存储器。 每个存储单元包括存储元件，例如一对交叉耦合的反相器，以及连接在存储节点之一和相反的反相器的输入之间的隔离栅极。 隔离栅极可以由并联连接的互补MOS晶体管实现，并且接收互补的隔离控制信号。 在读周期或写周期内未选择的列中，在字线通电之前，隔离栅极稍微关闭，并在字线断电或在字线断电之后导通。 通过隔离相反存储节点的一个输入，交叉耦合的反相器的反馈环路被破坏，从而降低了单元稳定性故障的可能性。

    Bit-by-bit write assist for solid-state memory
    6.
    发明授权
    Bit-by-bit write assist for solid-state memory 有权
    固态存储器的逐位写入辅助

    公开(公告)号：US08462542B2

    公开(公告)日：2013-06-11

    申请号：US12822706

    申请日：2010-06-24

    申请人： Xiaowei Deng

    发明人： Xiaowei Deng

    IPC分类号： G11C11/34

    CPC分类号： G11C11/412

    摘要： A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, that is connected in series with a pair of power switch transistors between a power supply node and ground. One of the power switch transistors is gated by a word line indicating selection of the row containing the cell, and the other is gated by a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to the cell, both power switch transistors are turned off, removing bias from the inverter that assists its change of state in a write operation. In other embodiments, a single power switch transistor gated by either a word line or a column select signal may be used.

    摘要翻译： 在每个存储器单元内实现写辅助电路的固态存储器。 每个存储单元包括诸如一对交叉耦合的反相器的存储元件，其与电源节点和地之间的一对功率开关晶体管串联连接。 功率开关晶体管中的一个由指示包含单元的行的选择的字线选通，另一个由指示在写周期中选择包含单元的列的列选择信号选通。 在对单元进行写操作时，两个电源开关晶体管关闭，从写入操作中去除有助于其改变状态的反相器的偏置。 在其他实施例中，可以使用由字线或列选择信号选通的单个功率开关晶体管。

    Method of Screening Static Random Access Memories for Unstable Memory Cells
    7.
    发明申请
    Method of Screening Static Random Access Memories for Unstable Memory Cells 有权
    筛选不稳定存储器单元的静态随机存取存储器的方法

    公开(公告)号：US20130028036A1

    公开(公告)日：2013-01-31

    申请号：US13189675

    申请日：2011-07-25

    申请人： Xiaowei Deng ,  Wah Kit Loh

    发明人： Xiaowei Deng ,  Wah Kit Loh

    IPC分类号： G11C29/08

    CPC分类号： G11C29/50 ,  G11C11/41

    摘要： A screening method for testing solid-state memories for the effects of long-term shift and random telegraph noise (RTN). In the context of static random access memories (SRAMs), each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a severe first guardband sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband are then repeatedly tested with the bias voltage at a second guardband, less severe than the first guardband; if the tested cells pass this second guardband, the suspect cells are considered to not be vulnerable to RTN effects. Over-screening due to an unduly severe guardband is avoided, while still screening vulnerable memories from the population.

    摘要翻译： 用于测试固态存储器用于长期移位和随机电报噪声（RTN）的影响的筛选方法。 在静态随机存取存储器（SRAM）的上下文中，阵列中的每个存储单元在强大的第一保护带处的偏置电压（例如，电池电源电压）进行功能测试，足以解决最坏的情况长期偏移， RTN效应。 然后，以第二防护带的偏置电压重复测试失效的第一保护带的电池，不如第一保护带严重; 如果测试的细胞通过第二个保护带，则认为可疑细胞不易受到RTN的影响。 避免由于过度严重的防护带过度检查，同时仍然对人口的脆弱记忆进行筛查。

    Margin testing of static random access memory cells
    9.
    发明授权
    Margin testing of static random access memory cells 有权
    静态随机存取存储单元的边缘测试

    公开(公告)号：US08228749B2

    公开(公告)日：2012-07-24

    申请号：US12794139

    申请日：2010-06-04

    申请人： Xiaowei Deng ,  Wah Kit Loh ,  Lakshmikantha V. Holla ,  Parvinder Kumar Rana

    发明人： Xiaowei Deng ,  Wah Kit Loh ,  Lakshmikantha V. Holla ,  Parvinder Kumar Rana

    IPC分类号： G11C29/50 ,  G11C11/40 ,  G11C7/12

    CPC分类号： G11C29/50 ,  G11C11/41

    摘要： A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.

    摘要翻译： 一种静态随机存取存储器（SRAM）及其对电池稳定性，写裕度和读取电流裕度的评估方法。 存储器被构造为使得位线预充电可被禁用，并且因此在存储器操作期间，每列单元的互补位线可以浮置。 通过对列的位线进行预充电，然后浮置位线来执行各种测试，并且当位线浮动时，使一个或多个所选单元的字线脉冲以使其中一个位线上的电压放电 。 然后将放电的位线电压施加到另一个单元，然后在正常读取操作中读取，以确定其状态是否由于放电的位线电压而改变。 存储器可以以这种方式表征电池稳定性，写入裕度和读取电流裕度; 该方法也可以适应于制造边界屏幕，或用于故障分析。