公开(公告)号：US06215429B1

公开(公告)日：2001-04-10

申请号：US09232221

申请日：1999-01-19

申请人： Jonathan Herman Fischer ,  Donald Raymond Laturell ,  Lane A. Smith ,  Paul David Hendricks ,  James M. Little

发明人： Jonathan Herman Fischer ,  Donald Raymond Laturell ,  Lane A. Smith ,  Paul David Hendricks ,  James M. Little

IPC分类号： H03M162

CPC分类号： H03H17/0411 ,  H03H17/0288

摘要： An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad. A RAM is used to store the state variables for the 2nd order biquadratic equations. The state variable RAM is reset by controlling the clear input of latches at an input and/or the output of the state variable RAM, and the state variable RAM is addressed by a delta counter which is independent of the particular number of filter channels or filter orders implemented. Test patterns may be inserted between functional blocks of an integrated circuit such as the disclosed audio codec by appropriate control of the preset and clear inputs to output latches of the functional blocks.

摘要翻译： 集成电路，例如 符合AC '97标准的音频编解码器包括数字滤波器和增益模块，包括多个通道的增益控制和多个数字滤波通道。 增益控制模块包括需要不同夹持长度的数据样本的溢出检查。 数字滤波器的每个通道包括有限脉冲响应（FIR）滤波器和无限脉冲响应（IIR）滤波器。 数字滤波主要在硬件上实现，与所需信道数量和/或独立于滤波所需的顺序无关。 因此，可以仅通过增加时钟速度而不改变数字滤波器设计来增加滤波器通道或附加滤波。 FIR滤波器能够复位每个帧，以防止在内部节点处产生DC积累。 IIR滤波器执行多个二阶二次方程，其总平均值为每二阶二进制数四个时钟周期。 RAM用于存储二阶二次方程的状态变量。 通过控制状态变量RAM的输入端和/或输出端的锁存器的清零输入来复位状态变量RAM，并且状态变量RAM通过与滤波器通道或滤波器的特定数量无关的增量计数器来寻址 订单执行。 可以通过适当地控制预设和清除输入来输出功能块的锁存器，将测试模式插入诸如公开的音频编解码器的集成电路的功能块之间。

公开(公告)号：US5999114A

公开(公告)日：1999-12-07

申请号：US976105

申请日：1997-09-16

申请人： Paul David Hendricks

发明人： Paul David Hendricks

IPC分类号： H03M3/02 ,  H03M1/20

CPC分类号： H03M3/334 ,  H03M3/332 ,  H03M3/43 ,  H03M3/454

摘要： A method of breaking up idle tones in a converter is used for gain scaling and summing of digital input signals. The invention achieves this object by introducing dither. Further, the invention optimizes the dither introduced by adapting the magnitude of the dither based on the value of the feedback gain factor of the converter. By adapting the dither in this way, the output idle channel noise can be essentially constant and independent of the scaling factor of the converter.

摘要翻译： 用于分解转换器中的空闲音调的方法用于数字输入信号的增益缩放和求和。 本发明通过引入抖动来实现该目的。 此外，本发明通过基于转换器的反馈增益因子的值来适应抖动的大小来优化所引入的抖动。 通过以这种方式适配抖动，输出空闲信道噪声基本上是恒定的，与转换器的缩放因子无关。

公开(公告)号：US5801558A

公开(公告)日：1998-09-01

申请号：US757059

申请日：1996-11-26

申请人： Ronald Lamar Freyman ,  Paul David Hendricks ,  Richard Muscavage

发明人： Ronald Lamar Freyman ,  Paul David Hendricks ,  Richard Muscavage

IPC分类号： H03K17/16 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0948

CPC分类号： H03K17/163

摘要： There is disclosed an integrated circuit includes an output driver circuit providing control of transition time from one state to another. The output driver includes first and second input transistors coupled to an input node at which data is received. First and second output transistors are coupled to an output node at which the data is presented when the output driver is enabled. The first input transistor is coupled to the first output transistor defining a first node. The second input transistor is coupled to the second output transistor defining a second node. First and second switching circuits are coupled between the first node and the second node. The first switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The first switching circuit exhibits a characteristic upon being switched from one of the first or second states to the other, such as from the first state to the second state, that impacts turn-on time of one of the first and second output transistors. The second switching circuit is switchable between a first state that isolates the first node from the second node, and a second state that couples the first node to the second node. The second switching circuit also exhibits a characteristic that upon being switched from one of the first and second states impacts turn-on time of the other of the first and second output transistors.

摘要翻译： 公开了一种集成电路，其包括输出驱动器电路，其提供从一个状态到另一个状态的转换时间的控制。 输出驱动器包括耦合到接收数据的输入节点的第一和第二输入晶体管。 第一和第二输出晶体管耦合到输出节点，在输出节点处，当输出驱动器被使能时，数据被呈现。 第一输入晶体管耦合到限定第一节点的第一输出晶体管。 第二输入晶体管耦合到限定第二节点的第二输出晶体管。 第一和第二开关电路耦合在第一节点和第二节点之间。 第一切换电路可以在将第一节点与第二节点隔离的第一状态和将第一节点耦合到第二节点的第二状态之间切换。 第一切换电路在从第一状态或第二状态之一转换为另一状态（例如从第一状态转换到第二状态时）具有影响第一和第二输出晶体管之一的导通时间的特性。 第二切换电路可以在将第一节点与第二节点隔离的第一状态和将第一节点耦合到第二节点的第二状态之间切换。 第二开关电路还具有当从第一和第二状态中的一个切换时影响第一和第二输出晶体管中的另一个的导通时间的特性。

公开(公告)号：US06408031B1

公开(公告)日：2002-06-18

申请号：US09428086

申请日：1999-10-27

申请人： Paul David Hendricks

发明人： Paul David Hendricks

IPC分类号： H04B1406

CPC分类号： H03H17/0411

摘要： A digital system for filtering a single bit input signal according to the transfer function H(z), wherein H(z) has a gain G, a pole at location b0, and a zero at location a0. The digital system filters the single bit input signal without using computationally expensive multibit multiplication. The digital system achieves these advantages with a digital circuit having a first gain stage generating a gain corrected signal, a delay element generating a delayed gain corrected signal, a feed-forward stage generating a feed-forward signal, and a summer for generating an output signal based upon the sum of the gain corrected signal, the delayed gain corrected signal and the feed-forward signal.

摘要翻译： 一种用于根据传递函数H（z）对单个位输入信号进行滤波的数字系统，其中H（z）具有增益G，位置b0处的极点和位置a0处的零点。 数字系统对单位输入信号进行滤波，而不用计算昂贵的多位乘法。 数字系统通过具有产生增益校正信号的第一增益级的数字电路，产生延迟增益校正信号的延迟元件，产生前馈信号的前馈级和用于产生输出的加法器来实现这些优点 基于增益校正信号，延迟增益校正信号和前馈信号之和的信号。