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公开(公告)号：US11742870B2
公开(公告)日：2023-08-29
申请号：US17807730
申请日：2022-06-19
申请人： ULTRALEAP LIMITED
CPC分类号： H03M1/0641 , H03M3/332
摘要： A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.
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2.发明申请公开(公告)号：US20150270847A1
公开(公告)日：2015-09-24
申请号：US14661388
申请日：2015-03-18
发明人： Ion Opris , Justin Seng
IPC分类号： H03M3/00
摘要： Apparatus and methods for analog-to-digital converters are provided. In an example, a sigma-delta analog-to-digital converter (ADC) can include a modulator configured to receive an analog signal and a decimation filter configured to provide a digital representation of the analog signal using an output of the modulator. In certain examples, the modulator can includes an integrator and a comparator od quantizer coupled to an output of the integrator. The comparator, in certain examples, can be configured to receive a second signal from the output of the integrator and to receive a plurality of dither signals, the dither signals can be configured to prevent limit cycles of the sigma-delta ADC.
摘要翻译： 提供了用于模数转换器的装置和方法。 在一个示例中，Σ-Δ模数转换器（ADC）可以包括被配置为接收模拟信号的调制器和被配置为使用调制器的输出来提供模拟信号的数字表示的抽取滤波器。 在某些示例中，调制器可以包括耦合到积分器的输出的积分器和比较器量子化器。 在某些示例中，比较器可被配置为从积分器的输出接收第二信号并且接收多个抖动信号，所述抖动信号可被配置为防止Σ-ΔADC的极限周期。
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公开(公告)号：US20130057419A1
公开(公告)日：2013-03-07
申请号：US13523592
申请日：2012-06-14
IPC分类号： H03M3/02
摘要： A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译： 具有多个输入通道的Δ-ΣA / D转换器包括量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。
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4.再颁专利Oversampling analog-to-digital converter and method with reduced chopping residue noise 有权过采样模数转换器和减少斩波残留噪声的方法公开(公告)号：USRE41830E1
公开(公告)日：2010-10-19
申请号：US12583668
申请日：2009-08-25
申请人： Shang-Yuan Chuang
发明人： Shang-Yuan Chuang
IPC分类号： H03M3/00
摘要： A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudo-random sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.
摘要翻译： Δ-Σ调制器包括斩波稳定的积分器，具有耦合到积分器的输出的输入的量化器，由切换的参考反馈电路控制并具有耦合到积分器的输入的输出的输入信号获取电路，以及 包括伪随机序列发生器并产生频率形状的伪随机时钟信号的频率形状的伪随机斩波时钟信号发生器电路。 复位电路耦合到伪随机序列发生器的复位输入，以与斩波稳定的Δ-Σ调制器的数字输出同步地复位，以防止由伪随机序列发生器的环绕操作引起的噪声。 逻辑电路响应于频率形状的伪随机时钟信号产生斩波时钟信号，并将其应用于积分器的各种输入开关和输出开关。
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5.发明授权Differential front-end continuous-time sigma-delta ADC using chopper stabilization 有权差分前端连续时间Σ-ΔADC使用斩波稳定公开(公告)号：US07193545B2
公开(公告)日：2007-03-20
申请号：US11228113
申请日：2005-09-16
申请人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
发明人： Paul John Morrow , Maria del Mar Chamarro Marti , Colin G. Lyden , Mike Dominic Keane , Robert W. Adams , Richard Thomas O'Brien , Paschal Thomas Minogue , Hans Johan Olaf Mansson
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.
摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。
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公开(公告)号：US20060170576A1
公开(公告)日：2006-08-03
申请号：US11047193
申请日：2005-01-31
申请人： Zhang Weibiao , James Hochschild
发明人： Zhang Weibiao , James Hochschild
IPC分类号： H03M3/00
摘要： A sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increase linearity of the converter. The dither is differentiated in multiple orders before being applied to the converter quantizer. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.
摘要翻译： 具有动态抖动的Σ-Δ转换器，其减少或去除空闲信道音调并增加转换器的线性度。 在施加到转换器量化器之前，抖动以多个阶数进行区分。 基于输入信号幅度动态地确定抖动的微分阶数和振幅，以获得抖动的最有效性。 动态抖动可用于模数转换器和数模转换器。
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7.发明申请Differential front-end continuous-time sigma-delta ADC using chopper stabilisation 有权差分前端连续时间Σ-ΔADC使用斩波稳定公开(公告)号：US20060139192A1
公开(公告)日：2006-06-29
申请号：US11228113
申请日：2005-09-16
申请人： Paul Morrow , Maria del Mar Chamarro Marti , Colin Lyden , Mike Keane , Robert Adams , Richard O'Brien , Paschal Minogue , Hans Mansson
发明人： Paul Morrow , Maria del Mar Chamarro Marti , Colin Lyden , Mike Keane , Robert Adams , Richard O'Brien , Paschal Minogue , Hans Mansson
IPC分类号： H03M3/00
摘要： A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency FS and the chopping switches can operate at FS or a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.
摘要翻译： 多位连续时间Σ-Δ模数转换器（ADC）具有接收模拟输入信号电流的差分输入级。 多位反馈电流数模转换器（IDAC）根据闪存ADC的数字反馈信号产生多电平反馈电流。 积分器具有差分输入，其通过多位IDAC产生的电流与输入信号电流的连续时间积分。 输入级还包括第一偏置电流源和在中等尺度条件下偏置输入级的第二偏置电流源。 第一求和节点连接到第一差分输入线，积分器的第一差分输入和第一输出分支。 第二求和节点连接到第二差分输入线，积分器和第二输出分支的第二差分输入。 一组斩波开关将偏置电流源以第一配置和第二反向配置交替地连接到求和节点。 转换器以频率F S S接收调制器时钟信号，并且斩波开关可以在F S或其二进制细分上工作。 积分放大器也可以斩波稳定。
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公开(公告)号：US06919832B2
公开(公告)日：2005-07-19
申请号：US10668296
申请日：2003-09-24
申请人： Todd Lee Brooks
发明人： Todd Lee Brooks
IPC分类号： H03M3/00
摘要： Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.
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公开(公告)号：US20050068212A1
公开(公告)日：2005-03-31
申请号：US10676320
申请日：2003-09-30
申请人： Henrik Jensen
发明人： Henrik Jensen
摘要： The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CTΔΣADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CTΔΣADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CTΔΣADC loop. In one embodiment of the invention, random noise is added to the quantizer input. In another embodiment, a relatively small amount of current is randomly added or subtracted in the feedback loop to randomize and de-correlate the quantization noise from the input signal while maintaining required signal to noise ratios.
摘要翻译： 本发明采用数字信号处理和模拟电路的混合来减少连续时间ΔΣ模数转换器（CTDeltaSigmaADC）中的杂散噪声。 具体地，将少量随机加性噪声（也称为抖动）引入到CTDeltaSigmaADC中，以通过使来自输入信号的量化噪声随机化和解相关而不显着降低SNR性能来改善线性行为。 在每个实施例中，数字电路用于产生抖动的期望随机性，去相关性和光谱形状，并且使用简单的模拟电路块来适当地缩放并将抖动注入到CTDeltaSigmaADC环路中。 在本发明的一个实施例中，随机噪声被加到量化器输入端。 在另一个实施例中，在反馈环路中随机地增加或减少相对较少量的电流，以便在保持所需的信噪比的同时使来自输入信号的量化噪声随机化和解相关。
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10.发明申请公开(公告)号：US20050040981A1
公开(公告)日：2005-02-24
申请号：US10767775
申请日：2004-01-30
申请人： Kevin Miller
发明人： Kevin Miller
摘要： In a modulator circuit, a mapping function is performed within a main feedback loop of the modulator, rather than after the feedback loop. In a high-fidelity digital modulator embodiment, pulse width modulation mapping generates a fairly large harmonic content when cascaded with the digital modulator circuit and tends to dramatically change the shape of the noise floor in the desired band, e.g. 0-40 kHz. Placing the mapping function within the modulator feedback loop tends to compensate for non-linear features of the mapping function, thus reducing harmonic generation and simplifying the task of suppressing harmonic generation to an acceptable level. In addition to reducing harmonic generation, this arrangement simplifies feedback processing and the accumulation of feedback information within various integrators in the modulator circuit.
摘要翻译： 在调制器电路中，在调制器的主反馈环路内执行映射函数，而不是在反馈环路之后执行。 在高保真数字调制器实施例中，当与数字调制器电路级联时，脉冲宽度调制映射产生相当大的谐波含量，并且倾向于显着地改变期望频带内的本底噪声的形状。 0-40 kHz。 将映射函数置于调制器反馈环路内趋于补偿映射函数的非线性特征，从而减少谐波产生，并简化将谐波产生抑制到可接受水平的任务。 除了减少谐波产生之外，这种布置简化了反馈处理和在调制器电路中的各种积分器内的反馈信息的累积。
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