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8 条记录 (耗时 0.014 秒)

    Phase lock loop and method for coded waveforms
    1.
    发明授权
    Phase lock loop and method for coded waveforms 有权
    锁相环和编码波形的方法

    公开(公告)号：US07209532B2

    公开(公告)日：2007-04-24

    申请号：US10107422

    申请日：2002-03-28

    申请人： Clifford Hessel ,  Paul E. Voglewede

    发明人： Clifford Hessel ,  Paul E. Voglewede

    IPC分类号： H03D3/24

    CPC分类号： H04L27/0014 ,  H04L2027/0024 ,  H04L2027/0055 ,  H04L2027/0077

    摘要： A communication system from maintaining synchronization includes a communication signal comprising a carrier and a data signal that is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. A delay circuit is placed in series with the quick decision circuit to compensate for the traceback delay in the Viterbi decoder. If the difference in the output signals of Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter. A synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected.

    摘要翻译： 保持同步的通信系统包括通信信号，该通信信号包括载波和从发射机发送到包括锁相环的接收机的数据信号。 接收机将维特比解码器的输出与快速判定电路的输出进行比较。 包含追溯的维特比解码器确定多个符号的最小聚合欧几里德距离。 快速判决电路确定单个符号的最小欧几里德距离，而不对码元进行解码。 延迟电路与快速判定电路串联放置以补偿维特比解码器中的回溯延迟。 如果维特比解码器和快速判定电路的输出信号的差大于预定的阈值，则防止锁相环中的相位误差信号更新锁相环滤波器。 如果检测到同步丢失，则同步丢失检测器也可用于防止相位误差信号更新锁相环滤波器。

    ARQ combining holdoff system and method
    3.
    发明授权
    ARQ combining holdoff system and method 失效

    公开(公告)号：US07036065B2

    公开(公告)日：2006-04-25

    申请号：US10098470

    申请日：2002-03-18

    申请人： Clifford Hessel ,  Paul E. Voglewede

    发明人： Clifford Hessel ,  Paul E. Voglewede

    IPC分类号： G06F11/00

    CPC分类号： H04L1/0061 ,  H03M13/33 ,  H03M13/3769 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/6306 ,  H03M13/6325 ,  H04L1/0047 ,  H04L1/0054 ,  H04L1/1845

    摘要： A system and method for demodulating a data packet in an automatic repeat request communication system is disclosed. Specifically, in a communication system that combines the energy of an initially transmitted data packet with the energy of a retransmitted version of the data packet, the inventive system and method measures the “usability” of the initially transmitted data packet that fails an error-checking procedure and the “usability” of a retransmitted version of the data packet. If the initially transmitted version and the retransmitted version of the data packet are both “usable”, the energies of the data packets are combined. The combined data packet is then subjected to the error-checking procedure. If the combined data packet fails the error-checking procedure, the energy of either the combined packet or the retransmitted packet is stored for later combination with a subsequently-retransmitted version of the data packet.

    Phase lock loop and method for coded waveforms
    6.
    发明授权
    Phase lock loop and method for coded waveforms 有权
    锁相环和编码波形的方法

    公开(公告)号：US07949082B2

    公开(公告)日：2011-05-24

    申请号：US11651566

    申请日：2007-01-10

    申请人： Clifford Hessel ,  Paul E. Voglewede

    发明人： Clifford Hessel ,  Paul E. Voglewede

    IPC分类号： H03D3/24

    CPC分类号： H04L27/0014 ,  H04L2027/0024 ,  H04L2027/0055 ,  H04L2027/0077

    摘要： A system and method is disclosed for maintaining synchronization in a communication system in which a signal is sent from a transmitter to a receiver which includes a phase lock loop. The receiver compares the output of a Viterbi decoder with the output of a quick decision circuit. The Viterbi decoder, which incorporates traceback, determines the minimum aggregate Euclidean distance for multiple symbols. The quick decision circuit determines the minimum Euclidean distance for a single symbol without decoding the symbol. If the difference in the output signals of the Viterbi decoder and the quick decision circuit is greater than a predetermined threshold, the phase error signal in the phase lock loop is prevented from updating the phase lock loop filter. A synchronization loss detector may also be used to prevent the phase error signal from updating the phase lock loop filter if synchronization loss is detected.

    摘要翻译： 公开了一种用于在通信系统中维持同步的系统和方法，其中信号从发射机发送到包括锁相环的接收机。 接收机将维特比解码器的输出与快速判定电路的输出进行比较。 包含追溯的维特比解码器确定多个符号的最小聚合欧几里德距离。 快速判决电路确定单个符号的最小欧几里德距离，而不对码元进行解码。 如果维特比解码器和快速判定电路的输出信号的差大于预定阈值，则防止锁相环中的相位误差信号更新锁相环滤波器。 如果检测到同步丢失，则同步丢失检测器也可用于防止相位误差信号更新锁相环滤波器。