公开(公告)号：US07103112B2

公开(公告)日：2006-09-05

申请号：US10011580

申请日：2001-12-04

申请人： Mark A. Webster ,  Paul J. Chiuchiolo ,  Harold P. Phares

发明人： Mark A. Webster ,  Paul J. Chiuchiolo ,  Harold P. Phares

IPC分类号： H04L27/36 ,  H04B3/04 ,  H04B3/14 ,  H04B1/76

CPC分类号： H04L25/03343 ,  H04L25/03159 ,  H04L2025/03414

摘要： A transmit processor that includes a transmit frequency domain equalizer (TX FEQ) that pre-compensates packets in the frequency domain to flatten transmit filter response to improve the spectral mask and reduce packet error rate (PER). The TX FEQ taps may be selected so that the average power at the output equalize the average power applied to the input. The TX FEQ may be designed to yield 64 QAM packets with no quantization distortion at the input of the an Inverse Fast Fourier Transform (IFFT) processor. The 64 QAM constellation map points and TX FEQ gain values are selected to avoid exceeding the bit resolution of the IFFT processor. The tones may be bound together into zones to reduce implementation complexity by reducing the number of TX FEQ taps.

摘要翻译： 一种发射处理器，其包括发射频域均衡器（TX FEQ），其对频域中的分组进行预补偿，以平坦化发射滤波器响应，以改善频谱掩模并降低分组差错率（PER）。 可以选择TX FEQ抽头，使得输出端的平均功率将施加到输入端的平均功率相等。 TX FEQ可以被设计为在快速傅里叶逆变换（IFFT）处理器的输入处产生64个QAM分组而没有量化失真。 选择64个QAM星座图和TX FEQ增益值以避免超过IFFT处理器的位分辨率。 通过减少TX FEQ抽头的数量，音调可以一起绑定到区域中以降低实现复杂度。

公开(公告)号：US06876319B2

公开(公告)日：2005-04-05

申请号：US10306020

申请日：2002-11-27

申请人： Mark A. Webster ,  Kent A. Ponton ,  Paul J. Chiuchiolo, Jr.

发明人： Mark A. Webster ,  Kent A. Ponton ,  Paul J. Chiuchiolo, Jr.

IPC分类号： H03C3/40 ,  H03D3/00 ,  H03H17/06 ,  H03M3/00

CPC分类号： H03H17/0275 ,  H03C3/40 ,  H03D3/006 ,  H03H17/0657 ,  H03H17/0664 ,  H03H2218/04

摘要： An integrated demodulator and decimator circuit including a selective digital sign inverter and a decimator. The sign inverter negates selected digital samples based on Weaver demodulation and outputs demodulated digital samples at a sample rate. The decimator is a symmetric half-band FIR filter, where the demodulated digital samples are sequentially shifted through filter taps at the sample rate. The decimator outputs real output values based on digital samples shifted into alternate taps and imaginary output values based on digital samples shifted into the center tap. An integrated modulator and interpolator circuit includes a symmetric half-band FIR filter interpolator and a digital sign inverter. The interpolator includes two polyphase filters and a multiplexer. A first polyphase filter filters real digital samples and a second filters imaginary digital samples. The multiplexer provides interpolated digital samples at four times the sample rate. The digital sign inverter negates selected digital samples according to Weaver modulation.

摘要翻译： 包括选择性数字符号反相器和抽取器的集成解调器和抽取器电路。 符号逆变器根据Weaver解调器对所选择的数字样本进行取反，并以采样率输出解调数字样本。 抽取器是对称半带FIR滤波器，其中解调的数字样本以采样率顺序地移动通过滤波器抽头。 抽取器基于基于移入中心抽头的数字样本的基于被替换为交替抽头的数字样本和虚数输出值而输出实际输出值。 集成调制器和内插器电路包括对称半带FIR滤波器内插器和数字符号逆变器。 内插器包括两个多相滤波器和多路复用器。 第一个多相滤波器滤除实数数字样本和第二个滤波器虚数字样本。 多路复用器提供四倍采样率的内插数字采样。 数字符号逆变器根据Weaver调制器对所选择的数字样本进行否定。

公开(公告)号：US06973296B2

公开(公告)日：2005-12-06

申请号：US10011794

申请日：2001-12-04

申请人： Mark A. Webster ,  Paul J. Chiuchiolo ,  Albert L. Garrett

发明人： Mark A. Webster ,  Paul J. Chiuchiolo ,  Albert L. Garrett

IPC分类号： H04L25/03 ,  H04L27/26 ,  H04B1/10

CPC分类号： H04L25/03159 ,  H04L27/2613 ,  H04L27/2657 ,  H04L27/2695 ,  H04L2025/03414

摘要： A wireless receiver including a receive chain, a synchronization processor, a memory, a combiner and a soft decision processor. The synchronization processor determines a frequency response of the wireless channel using synchronization data transmitted in the wireless channel. The memory stores a compensation vector indicative of a frequency response of receive chain filtering. The combiner combines the compensation vector with the wireless channel frequency response to provide a compensated frequency response. The soft decision processor uses the compensated frequency response to evaluate data decisions. The compensation vector is based on measurement or estimation of the frequency response of the receive chain. The combiner may be based on multiplication or addition. The wireless receiver may include an FEQ. The synchronization processor generates FEQ coefficients for programming the FEQ taps. The FEQ provides an equalized data value and a compensated frequency response value to the soft decision processor for each sub-carrier.

摘要翻译： 一种包括接收链，同步处理器，存储器，组合器和软判决处理器的无线接收器。 同步处理器使用在无线信道中发送的同步数据来确定无线信道的频率响应。 存储器存储指示接收链过滤的频率响应的补偿向量。 组合器将补偿矢量与无线信道频率响应相结合，以提供补偿的频率响应。 软决策处理器使用经补偿的频率响应来评估数据决策。 补偿矢量基于接收链的频率响应的测量或估计。 组合器可以基于乘法或加法。 无线接收机可以包括FEQ。 同步处理器产生用于对FEQ抽头进行编程的FEQ系数。 FEQ为每个子载波提供均衡的数据值和补偿的频率响应值给软判决处理器。