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    Set-associative cache memory having variable time decay rewriting algorithm
    4.
    发明授权
    Set-associative cache memory having variable time decay rewriting algorithm 失效
    具有可变时间衰减重写算法的集合相关缓存存储器

    公开(公告)号：US06732238B1

    公开(公告)日：2004-05-04

    申请号：US10167133

    申请日：2002-06-10

    申请人： Marc Alan Evans ,  Pavlos Konas

    发明人： Marc Alan Evans ,  Pavlos Konas

    IPC分类号： G06F1200

    CPC分类号： G06F12/123 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/128

    摘要： A set-associative structure replacement algorithm is particularly beneficial for irregular set-associative structures which may be affected by different access patterns, and different associativities available to be replaced on any given access. According to certain aspects, methods and apparatuses implement a novel decay replacement algorithm that is particularly beneficial for irregular set-associative structures. An embodiment apparatus includes set-associative structures having decay information stored therein, as well as update/replacement logic to implement replacement algorithms for translation lookup buffers (TLBS) and caches that vary in the number of associativities; have unbalanced associativity sizes, e.g., associativities can have different numbers of indices; and can have varying replacement criteria. The implementation apparatuses and methods provide good performance, on the level of LRU, random and clock algorithms; and is efficient and scalable.

    摘要翻译： 集合关联结构替换算法对于可能受不同访问模式影响的不规则集合关联结构以及可在任何给定访问上被替换的不同关联特别有益。 根据某些方面，方法和装置实现对于不规则集合关联结构特别有利的新型衰减替换算法。 实施例装置包括具有存储在其中的衰减信息的集合关联结构，以及更新/替换逻辑，以实现在关联数量上变化的翻译查找缓冲器（TLBS）和高速缓存的替换算法; 具有不平衡的缔合性大小，例如，关联性可以具有不同数量的索引; 并且可以具有不同的替换标准。 实现装置和方法在LRU，随机和时钟算法的水平上提供了良好的性能; 并且是高效和可扩展的。

    Configurable memory management unit
    6.
    发明授权
    Configurable memory management unit 有权
    可配置内存管理单元

    公开(公告)号：US06854046B1

    公开(公告)日：2005-02-08

    申请号：US10213370

    申请日：2002-08-05

    申请人： Marc A. Evans ,  Earl A. Killian ,  Pavlos Konas

    发明人： Marc A. Evans ,  Earl A. Killian ,  Pavlos Konas

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1036

    摘要： An MMU provides services at a cost more directly proportional to the needs of the system. According to one aspect, the MMU provides both address translation and sophisticated protection capabilities. Translation and protection are desirable when applications running on the processor are not completely debugged or trustable, for example. According to another aspect, a system for configuring the MMU design according to user specifications and system needs is provided. The MMU configurability aspects enable the system designer to configure MMUs having run-time programmability features that span the range from completely static to completely dynamic. In addition, the MMU can be configured to support variable page sizes, multiple protection and sharing rings, demand paging, and hardware TLB refill, for example.

    摘要翻译： MMU以与系统需求成正比的成本提供服务。 根据一方面，MMU提供地址转换和复杂的保护能力。 例如，在处理器上运行的应用程序未被完全调试或可信任的情况下，翻译和保护是可取的。 根据另一方面，提供了一种用于根据用户规格和系统需要配置MMU设计的系统。 MMU可配置性方面使系统设计人员能够配置具有跨越从完全静态到完全动态的范围的运行时可编程性功能的MMU。 此外，MMU可以配置为支持可变页大小，多重保护和共享环，请求分页和硬件TLB重新填充。

    Abstraction of configurable processor functionality for operating systems portability
    7.
    发明授权
    Abstraction of configurable processor functionality for operating systems portability 有权
    抽象可配置的处理器功能，用于操作系统的可移植性

    公开(公告)号：US06763327B1

    公开(公告)日：2004-07-13

    申请号：US09506433

    申请日：2000-02-17

    申请人： Christopher Mark Songer ,  Pavlos Konas ,  Marc E. Gauthier ,  Kevin C. Chea

    发明人： Christopher Mark Songer ,  Pavlos Konas ,  Marc E. Gauthier ,  Kevin C. Chea

    IPC分类号： G06F1750

    CPC分类号： G06F9/45533 ,  G06F9/45504 ,  G06F9/45541

    摘要： A hardware abstraction layer operates as a system architectural layer between a real-time operating system and an underlying configurable processor. The hardware abstraction layer provides an abstraction of processor-specific functionality to the operating system. In particular, it abstracts configurable processor features visible to the operating system to provide a uniform, standardized interface between the operating system and the configurable processor on which it runs. Thus, an operating system running on top of the hardware abstraction layer will work on all configurations of the processor which differ from one another only in the configuration parameters covered by the hardware abstraction layer. The hardware abstraction layer may be generated using the same information that is used to describe the features being configured in the configurable processor. Automatic generation of the HAL greatly eases use of the HAL and the configurable processor, since the user is not required to manually write the HAL or adapt an existing one based on the processor configuration parameters.

    摘要翻译： 硬件抽象层作为实时操作系统和底层可配置处理器之间的系统架构层运行。 硬件抽象层为操作系统提供了处理器专用功能的抽象。 特别地，它抽象出操作系统可见的可配置处理器功能，以在操作系统和其所运行的可配置处理器之间提供统一的标准化接口。 因此，在硬件抽象层之上运行的操作系统将仅在硬件抽象层覆盖的配置参数中彼此不同的处理器的所有配置上起作用。 可以使用用于描述在可配置处理器中配置的特征的相同信息来生成硬件抽象层。 自动生成HAL大大简化了HAL和可配置处理器的使用，因为用户不需要手动写入HAL或根据处理器配置参数来调整现有的HAL。