公开(公告)号：US07937559B1

公开(公告)日：2011-05-03

申请号：US11761322

申请日：2007-06-11

Applicant: Akilesh Parameswar ,  James Alexander Stuart Fiske ,  Ricardo E. Gonzalez

Inventor： Akilesh Parameswar ,  James Alexander Stuart Fiske ,  Ricardo E. Gonzalez

IPC: G06F9/00

CPC classification number: G06F9/30149 ,  G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3873 ,  G06F9/3885 ,  G06F9/3887

Abstract: A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.

Abstract translation: 处理器生成系统包括描述具有三种指令大小的处理器的能力。 在一个示例实现中，指令可以是16位，24位和64位。 这使得可以利用架构中的并行性的新系列架构。 特别地，这使得能够生成VLIW架构。 根据另一方面，处理器生成器允许设计者向处理器添加可配置数量的加载/存储单元。 为了适应多个加载/存储单元，连接到处理器的本地存储器可以具有多个读取和写入端口（每个加载/存储单元一个）。 这进一步允许本地存储器以任何任意连接拓扑连接。 自动生成连接盒硬件，根据配置，在加载/存储单元和本地存储器之间提供接口。

公开(公告)号：US07437700B2

公开(公告)日：2008-10-14

申请号：US11281217

申请日：2005-11-16

Applicant: Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F17/50

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract translation: 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US20060101369A1

公开(公告)日：2006-05-11

申请号：US11281217

申请日：2005-11-16

Applicant: Albert Wang ,  Richard Ruddell ,  David Goodwin ,  Earl Killian ,  Nupur Bhattacharyya ,  Marines Medina ,  Walter Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Songer ,  Akilesh Parameswar ,  Dror Maydan ,  Ricardo Gonzalez

Inventor： Albert Wang ,  Richard Ruddell ,  David Goodwin ,  Earl Killian ,  Nupur Bhattacharyya ,  Marines Medina ,  Walter Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Songer ,  Akilesh Parameswar ,  Dror Maydan ,  Ricardo Gonzalez

IPC: G06F17/50

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract translation: 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US08161432B2

公开(公告)日：2012-04-17

申请号：US12248890

申请日：2008-10-09

Applicant: Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F17/50

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract translation: 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US20090125866A1

公开(公告)日：2009-05-14

申请号：US12270498

申请日：2008-11-13

Applicant: ALBERT REN-RUI WANG ,  RICHARD RUDDELL ,  DAVID WILLIAM GOODWIN ,  EARL A. KILLIAM ,  NUPUR BHATTACHARYYA ,  MARINES PUIG MEDINA ,  WALTER DAVID LICHTENSTEIN ,  PAVLOS KONAS ,  RANGARAJAN SRINIVASAN ,  CHRISTOPHER MARK SONGER ,  AKILESH PARAMESWAR ,  DROR E. MAYDAN ,  RICARDO E. GONZALEZ

Inventor： ALBERT REN-RUI WANG ,  RICHARD RUDDELL ,  DAVID WILLIAM GOODWIN ,  EARL A. KILLIAM ,  NUPUR BHATTACHARYYA ,  MARINES PUIG MEDINA ,  WALTER DAVID LICHTENSTEIN ,  PAVLOS KONAS ,  RANGARAJAN SRINIVASAN ,  CHRISTOPHER MARK SONGER ,  AKILESH PARAMESWAR ,  DROR E. MAYDAN ,  RICARDO E. GONZALEZ

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract translation: 一种用于将包含要印刷在晶片上的特征的目标图案分解为多个图案的方法。 该方法包括以下步骤：将目标图案分割成多个贴片; 识别每个补丁内的违反最小间距要求的关键特征; 为具有关键特征的多个补丁中的每一个生成关键组图，其中给定补丁的关键组图定义给定补丁内的关键特征的着色方案，并且关键组图识别延伸到相邻补丁中的关键特征 给给定补丁; 为目标模式生成全局关键组图，其中全局关键组图包括多个补丁中的每一个的关键组图，以及延伸到相邻补丁中的特征的标识; 并基于由全局关键组图定义的着色方案着色目标图案。

公开(公告)号：US09582278B2

公开(公告)日：2017-02-28

申请号：US12248883

申请日：2008-10-09

Applicant: Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F17/50 ,  G06F9/30

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract translation: 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US20090177876A1

公开(公告)日：2009-07-09

申请号：US12248890

申请日：2008-10-09

Applicant: Albert Ren-Rui WANG ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui WANG ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F9/00

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

公开(公告)号：US20090172630A1

公开(公告)日：2009-07-02

申请号：US12248883

申请日：2008-10-09

Applicant: Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F17/50

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract translation: 用于生成处理器硬件的系统支持用于处理器指令集的显着扩展的语言，其中设计者仅指定新指令的语义，并且系统生成其他逻辑。 扩展语言提供了添加处理器状态，包括寄存器文件和在该状态下操作的指令。 该语言还提供了要添加到编译器中以表示添加的状态的新数据类型。 它允许单独指定参考语义和指令实现，并使用它来自动进行设计验证。 另外，系统从语言规范生成格式化指令集文档。

公开(公告)号：US07036106B1

公开(公告)日：2006-04-25

申请号：US09506502

申请日：2000-02-17

Applicant: Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

Inventor： Albert Ren-Rui Wang ,  Richard Ruddell ,  David William Goodwin ,  Earl A. Killian ,  Nupur Bhattacharyya ,  Marines Puig Medina ,  Walter David Lichtenstein ,  Pavlos Konas ,  Rangarajan Srinivasan ,  Christopher Mark Songer ,  Akilesh Parameswar ,  Dror E. Maydan ,  Ricardo E. Gonzalez

IPC: G06F17/50

CPC classification number: G06F9/30167 ,  G06F9/30145 ,  G06F17/5045

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.