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1.发明授权Method and apparatus for determining the position of a mobile communication device 失效用于确定移动通信设备的位置的方法和装置公开(公告)号：US06801782B2
公开(公告)日：2004-10-05
申请号：US09777625
申请日：2001-02-06
IPC分类号： H04Q700
CPC分类号： H04W64/00 , G01S5/021 , G01S5/0215 , G01S5/0221 , G01S5/0294 , G01S5/14 , G01S13/46 , G01S2013/466
摘要： A position location communication system determines the position of a mobile master radio using a round-trip messaging scheme in which the time of arrive (TOA) of ranging signals is accurately determined to yield the range estimates required to calculate the position of the mobile radio. The master radio transmits ranging signals to plural reference radios which respond by transmitting reply ranging signals. Upon reception of the reply ranging signal, the master radio determines the range to the reference radio from the signal propagation time. Any combination of fixed or mobile radios having known positions can be used as the reference radios for another mobile radio in the system. Individual radios do not need to be synchronized to a common time reference, thereby eliminating the need for highly accurate system clocks. Errors in TOA estimates are minimized by performing internal delay calibration, Doppler compensation, leading-edge-of-the-signal curve fitting and frequency diversity techniques.
摘要翻译： 位置定位通信系统使用其中准确地确定测距信号的到达时间（TOA）的往返消息方式来确定移动主控无线电的位置，以产生计算移动无线电的位置所需的范围估计。 主无线电发送测距信号到通过发送应答测距信号进行响应的多个参考无线电。 在接收到应答测距信号时，主无线电从信号传播时间确定到参考无线电的范围。 具有已知位置的固定或移动无线电的任何组合可用作系统中另一移动无线电的参考无线电。 单个无线电不需要与公共时间参考同步，从而不需要高精度的系统时钟。 通过执行内部延迟校准，多普勒补偿，信号前沿曲线拟合和频率分集技术，TOA估计的误差被最小化。
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2.发明授权Local and remote echo canceling apparatus particularly adapted for use in a full duplex modem 失效本地和远程回声消除装置，特别适用于全双工调制解调器
公开(公告)号：US5418778A
公开(公告)日：1995-05-23
申请号：US98639
申请日：1993-07-28
IPC分类号： H04B3/23
CPC分类号： H04B3/237
摘要： An echo cancellation apparatus is included in a variable rate modem. The echo cancellation apparatus includes a local echo canceler, a remote echo canceler and a quadrature echo canceler unit. The local and remote echo cancelers both operate to cancel echoes in a similar manner employing topped delay lines or transversal filters wherein the taps of each delay line are adjusted to accommodate both local and remote echo cancellation. The local echo canceler and the remote echo canceler share many programs in common. However, the remote echo canceler operates with a phase lock loop which essentially derives a signal obtained from the quadrature and local echo cancelers which signal is further correlated with the output residuals from the local echo canceler to develop samples applied to the remote echo canceler and to derive a frequency which is indicative of a offset carrier frequency to enable the remote echo canceler to cancel remote echoes. Remote echoes are due to frequency shifts occurring remote from the modem, such as those caused by changes in satellite positions or changes in frequency sources. The remote echo canceler operates to cancel echoes which are greater than 15 milliseconds in delay, as compared to local echoes, which are canceled by the local echo canceler responding to echoes which are delayed 15 milliseconds or less.
摘要翻译： 回波消除装置包括在可变速率调制解调器中。 回波消除装置包括本地回波消除器，远端回波消除器和正交回波消除器单元。 本地和远程回波消除器都以采用顶部延迟线或横向滤波器的类似方式来消除回波，其中每个延迟线的抽头被调节以适应本地和远程回波消除。 本地回波消除器和远程回波消除器共享许多程序。 然而，远程回波消除器通过锁相环工作，其基本上导出从正交和本地回波消除器获得的信号，该信号与来自本地回波消除器的输出残差进一步相关，以开发施加到远端回波消除器的采样， 导出表示偏移载波频率以使远程回波消除器能够取消远程回波的频率。 远程回波是由于远离调制解调器的频移，例如由卫星位置变化或频率变化引起的频移。 与局部回波相比，远程回波消除器操作以消除延迟大于15毫秒的回波，本地回波抵消延迟15毫秒或更短的回波。
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公开(公告)号：US5177734A
公开(公告)日：1993-01-05
申请号：US624570
申请日：1990-12-10
申请人： Peter Cummiskey , Marvin Epstein , Paul A. Gilmour , Richard Kim
发明人： Peter Cummiskey , Marvin Epstein , Paul A. Gilmour , Richard Kim
摘要： Multirate wire line modem apparatus operable at either of two rates in either transmission or reception modes is provided according to the teachings of the instant invention. Full duplex operation and echo cancellation are utilized for both voice and data. Structurally an IOP processor acts as a system controller in controlling transmission and reception digital signal processors which provide the independent transmission and reception functions of the resulting multirate modem apparatus.
摘要翻译： 根据本发明的教导，提供以传输或接收模式中的两种速率中的任一种操作的多速率有线线路调制解调器装置。 全双工操作和回声消除用于语音和数据。 结构上，IOP处理器用作控制发送和接收数字信号处理器的系统控制器，其提供所得到的多速率调制解调器装置的独立发送和接收功能。
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公开(公告)号：US5506781A
公开(公告)日：1996-04-09
申请号：US253722
申请日：1994-06-03
CPC分类号： H04B7/2125
摘要： A system and method for maintaining a precise time standard among a system of orbiting satellites is disclosed. In an illustrative embodiment, atomic clock data is circulated among the satellites via RF crosslinks. Each satellite uses the received data as input to a Kalman process which acts to minimize the mean squared error among the satellite clocks to form a set of "ensemble clocks". The resulting ensemble clock values are then transmitted to an earth station where an offset between the ensemble clocks and Universal Time is computed. The offset is transmitted from the earth station to the satellites where it is used by the satellites to lock their on-board clocks to Universal Time, thereby creating a corrected system time. The corrected system time is transmitted, via RF crosslinks, to satellites not having operational on-board clocks. The satellites without atomic clocks employ phase locked loops to anchor their clocks to the corrected system time as it is received over the crosslinks.
摘要翻译： 公开了一种在轨道卫星系统中保持精确的时间标准的系统和方法。 在说明性实施例中，原子钟数据通过RF交联在卫星之间循环。 每个卫星使用接收的数据作为卡尔曼过程的输入，其用于最小化卫星时钟之间的均方误差以形成一组“合成时钟”。 然后将所得到的集合时钟值发送到地球站，其中计算集成时钟和通用时间之间的偏移。 偏移量从地球站传输到由卫星使用的卫星，将其车载时钟锁定到通用时间，从而创建校正的系统时间。 校正的系统时间通过RF交联传输到不具有操作板载时钟的卫星。 没有原子钟的卫星采用锁相环来将它们的时钟锚定到校正的系统时间，因为它被接收在交联上。
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公开(公告)号：US5005168A
公开(公告)日：1991-04-02
申请号：US189497
申请日：1988-05-02
申请人： Peter Cummiskey , Marvin Epstein , Paul A. Gilmour , Richard Kim
发明人： Peter Cummiskey , Marvin Epstein , Paul A. Gilmour , Richard Kim
摘要： Multirate wire line modem apparatus operable at either of two rates in either transmission or reception modes is provided according to the teachings of the instant invention. Full duplex operation and echo cancellation are utilized for both voice and data. Structurally an IOP processor acts as a system controller in controlling transmission and reception digital signal processors which provide the independent transmission and reception functions of the resulting multirate modem apparatus.
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公开(公告)号：US4353128A
公开(公告)日：1982-10-05
申请号：US161203
申请日：1980-06-19
申请人： Peter Cummiskey
发明人： Peter Cummiskey
CPC分类号： H04L5/225
摘要： A data communication arrangement is disclosed for multiplexing an asynchronous binary data signal with a synchronous binary data signal by the timely insertion of an extra data bit in selected synchronous data words and by delaying the transmission of the resulting multiplexed data words. The extra data bit is generated when a binary level transition occurs in the asynchronous binary data signal. The transmission of the multiplexed data word is delayed a fixed amount of time relative to the binary level transition of the asynchronous signal to preserve the timing between transitions in the asynchronous signal. The received multiplexed data words are demultiplexed into a synchronous and asynchronous binary data signals. The demultiplexed asynchronous binary data signal emerges having transition timing which is the same as the transition timing of the original asynchronous binary data signal.
摘要翻译： 公开了一种数据通信装置，用于通过在选定的同步数据字中及时插入额外的数据位并通过延迟所生成的多路复用数据字的传输来将异步二进制数据信号与同步二进制数据信号进行多路复用。 当异步二进制数据信号中发生二进制电平转换时，产生额外的数据位。 多路复用数据字的传输相对于异步信号的二进制电平转换被延迟固定的时间量，以保持异步信号中的转换之间的定时。 所接收的复用数据字被解复用为同步和异步二进制数据信号。 解复用的异步二进制数据信号出现具有与原始异步二进制数据信号的转换定时相同的转换定时。
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公开(公告)号：US4344180A
公开(公告)日：1982-08-10
申请号：US161170
申请日：1980-06-19
申请人： Peter Cummiskey
发明人： Peter Cummiskey
CPC分类号： H04J3/0602
摘要： A frame synchronization arrangement is disclosed for use in a digital data transmission system which utilizes a redundant data word transmission. A selected data word of each frame of data having a fixed location relative to the frame boundary is transmitted twice to provide a framing signal for the receiver circuit. At the receiver circuit the data is shifted through a shift register where a comparator checks predetermined locations of the shift register for redundant data words in the received data stream. Once the redundant data words are detected a valid word received signal is generated. The existence of the valid word received signal together with the known relationship between the location of the redundant word and the frame boundary is used to provide a framing signal.
摘要翻译： 公开了一种用于使用冗余数据字传输的数字数据传输系统中的帧同步装置。 发送两次具有相对于帧边界的固定位置的每帧数据的选择的数据字，以提供接收机电路的成帧信号。 在接收器电路处，数据通过移位寄存器移位，其中比较器检查移位寄存器的预定位置，以便接收数据流中的冗余数据字。 一旦检测到冗余数据字，就产生有效的字接收信号。 使用有效字接收信号的存在以及冗余字的位置与帧边界之间的已知关系来提供成帧信号。
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公开(公告)号：US4306304A
公开(公告)日：1981-12-15
申请号：US062425
申请日：1979-07-31
申请人： Leslie A. Baxter , Peter Cummiskey
发明人： Leslie A. Baxter , Peter Cummiskey
CPC分类号： H04L12/422 , H04J3/0626 , H04Q11/04
摘要： There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to add or subtract delay as necessary. A FIFO register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the FIFO register. If a unique frame bit is not received in the anticipated position the output FIFO clock skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.
摘要翻译： 公开了一种用于控制围绕闭环通信系统的同步的数字环路电路。 控制电路被设计为自动调整回路的延迟以保持恒定的帧位长度，而不考虑连接到回路中的站数。 由于从循环中添加或减少站，系统将根据需要进行加法或减法延迟。 具有等于帧大小的位容量的FIFO寄存器被串行地插入到环路中，并且使用单独的时钟来控制FIFO寄存器的输入和输出。 如果在预期位置没有接收到唯一的帧位，则输出FIFO时钟跳过每帧一个计数，从而将延迟添加到循环。 环路控制电路适用于成帧位在单独信道上的情况，并且当成帧位在实际数据信道上时。
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公开(公告)号：US4229815A
公开(公告)日：1980-10-21
申请号：US962226
申请日：1978-11-20
申请人： Peter Cummiskey
发明人： Peter Cummiskey
CPC分类号： H04L25/05
摘要： The disclosed full duplex bit synchronous data rate buffer (15) adapts high speed burst data signals for transmission over low speed data facilities. The data rate buffer (15) includes a buffer control circuit (201-205, 105) for interactively controlling a first data buffer (101) for down-converting the high speed signals (107) to low speed signals (109) and a second data buffer (102) for up-converting low speed data signals (108) to high speed burst data signals (106). The data rate buffer (15) accepts random changes in the length of each high speed burst data signal without a loss in bit synchronism and adjusts for changes in the number of burst data signals contained in each frame.
摘要翻译： 所公开的全双工位同步数据速率缓冲器（15）适应高速突发数据信号以在低速数据设备上传输。 数据速率缓冲器（15）包括缓冲器控制电路（201-205,105），用于交互地控制用于将高速信号（107）下变频为低速信号（109）的第一数据缓冲器（101） 数据缓冲器（102），用于将低速数据信号（108）上变频到高速脉冲数据信号（106）。 数据速率缓冲器（15）接受每个高速脉冲串数据信号的长度的随机变化，而不产生位同步丢失，并且调整包含在每个帧中的突发数据信号的数量的变化。
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