公开(公告)号：US20120113326A1

公开(公告)日：2012-05-10

申请号：US12939921

申请日：2010-11-04

申请人： Jyothsna Nagaraja ,  Peter Dean Swartz

发明人： Jyothsna Nagaraja ,  Peter Dean Swartz

IPC分类号： H04N5/14 ,  H04N7/12

CPC分类号： H04N5/145 ,  H04N19/53

摘要： The present disclosure provides a system and method for detecting motion vectors in an image frame using a recursive hierarchical process with a non-rasterized vector-scanning motion to reduce erroneous motion vectors in an image frame of a digital video sequence. In general, a resolution hierarchy is generated for an image frame, wherein the resolution hierarchy comprises the original image frame and one or more copy image frames each having a different, lower resolution than the original image frame. Each image frame in the hierarchy is partitioned into image patches disposed in columns and rows, and the image patches are scanned in a non-rasterized motion to detect motion vectors in each image patch. The disclosed system and method provides faster convergence and improved accuracy by converging motion vectors in multiple directions and minimizing erroneous motion vectors in the image sequence.

摘要翻译： 本公开提供一种用于使用具有非光栅化矢量扫描运动的递归分级处理来检测图像帧中的运动矢量的系统和方法，以减少数字视频序列的图像帧中的错误运动矢量。 通常，为图像帧生成分辨率层次，其中分辨率层级包括原始图像帧和每个具有与原始图像帧不同的较低分辨率的一个或多个复制图像帧。 层次结构中的每个图像帧被分割成排列成列和行的图像块，并且以非光栅化运动扫描图像块以检测每个图像块中的运动矢量。 所公开的系统和方法通过在多个方向上收敛运动矢量并且使图像序列中的错误运动矢量最小化来提供更快的收敛和提高的精度。

公开(公告)号：US07341499B2

公开(公告)日：2008-03-11

申请号：US10755519

申请日：2004-01-12

申请人： Anatol Wizenberg ,  Peter Dean ,  Wai Bun Choi ,  Ming To Chan ,  Lai Hong Man

发明人： Anatol Wizenberg ,  Peter Dean ,  Wai Bun Choi ,  Ming To Chan ,  Lai Hong Man

IPC分类号： A63H33/02

CPC分类号： A63G17/00

摘要： A toy glider including a shaft, a roller attached to a first end of the shaft, and a housing attached to a second opposing end of the shaft. The roller, a front end portion of the housing, and other portions of the toy glider are interchangeable to create a variety of different designs.

摘要翻译： 一种玩具滑翔机，其包括轴，附接到所述轴的第一端的滚子以及附接到所述轴的第二相对端的壳体。 滚子，外壳的前端部分和玩具滑翔机的其他部分是可互换的，以产生各种不同的设计。

公开(公告)号：US07158186B2

公开(公告)日：2007-01-02

申请号：US10446330

申请日：2003-05-27

申请人： Steve Selby ,  Peter Dean Swartz

发明人： Steve Selby ,  Peter Dean Swartz

IPC分类号： H04N7/01

CPC分类号： H04N7/0112 ,  G09G5/005 ,  G09G2310/0224 ,  G09G2360/02 ,  H04N5/147 ,  H04N7/012 ,  H04N7/0132

摘要： A video display system is disclosed. The video display system comprises a display generator for providing a display timing signal and a frame rate converter for receiving input video data, input video timing, and for providing output video data. The system includes a control logic for receiving a frame rate indication signal, the video input timing and the display timing signal. The control logic changes the display frame rate of the display generator in accordance with the native frame rate of the program, and in such a way as to maintain a stable image throughout.

摘要翻译： 公开了一种视频显示系统。 视频显示系统包括用于提供显示定时信号的显示发生器和用于接收输入视频数据，输入视频定时和用于提供输出视频数据的帧速率转换器。 该系统包括用于接收帧速率指示信号，视频输入定时和显示定时信号的控制逻辑。 控制逻辑根据程序的本地帧速率改变显示生成器的显示帧速率，并且以这样的方式保持整个图像的稳定图像。

公开(公告)号：US06829731B1

公开(公告)日：2004-12-07

申请号：US09638757

申请日：2000-08-14

申请人： Peter Dean LaFauci ,  Rhonda Gurganious Mitchell ,  Jeffrey Richard Summers

发明人： Peter Dean LaFauci ,  Rhonda Gurganious Mitchell ,  Jeffrey Richard Summers

IPC分类号： G05F1100

CPC分类号： G06F11/3696 ,  G06F11/3684

摘要： A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.

摘要翻译： 一种用于自动创建逻辑设计测试用例的方法和系统。 在用户界面中向测试用例设计者提供表征总线架构的综合总线事务。 设计者可以通过接口输入与特定待测设计（DUT）相对应的输入。 接口处理输入以自动生成与特定DUT相对应的配置文件。 配置文件可以由生成器程序来处理，以自动生成包括针对特定DUT定制的一个或多个总线事务的测试用例。

公开(公告)号：US06587905B1

公开(公告)日：2003-07-01

申请号：US09606463

申请日：2000-06-29

申请人： Anthony Correale, Jr. ,  Richard Gerard Hofmann ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

发明人： Anthony Correale, Jr. ,  Richard Gerard Hofmann ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged. A corresponding Auxiliary_(read or write) command is routed to the slave units to notify the units when to route normal read or write data to an idle bus. The bus controller may use this added feature to optimize the available bandwidth of independent read and write data busses up to the limit where a read or write bandwidth may be two times that available if the read and write data buses were used only for their normal traffic.

摘要翻译： 具有独立读写数据总线的高性能集成电路（IC）使得能够在耦合到总线的器件之间实现全面同时的读和写数据传输。 多个主设备和多个从设备使用总线控制器和总线仲裁器的资源进行通信。 具有独立且独立仲裁的单独的读写数据总线允许来自不同设备的读取和写入同时发生。 许多高性能IC，如片上系统（SOC），具有与中央处理单元（CPU）通信的许多不同功能单元。 许多这样的CPU具有在某些应用中可能导致独立总线上的读取和写入流量之间的不平衡的架构。 主设备和从设备包含辅助内部读和写数据总线进行复用，使得读或写数据可以互换。 相应的辅助（读或写）命令被路由到从单元，以通知单元何时将正常读或写数据传送到空闲总线。 总线控制器可以使用这个附加功能来优化独立的读和写数据总线的可用带宽，直到只有在读写数据总线仅用于其正常业务时，读或写带宽可能是可用的两倍 。

公开(公告)号：US06430641B1

公开(公告)日：2002-08-06

申请号：US09304939

申请日：1999-05-04

申请人： Richard Gerard Hofmann ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

发明人： Richard Gerard Hofmann ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

IPC分类号： G06F1338

CPC分类号： G06F13/364

摘要： Methods, arbiters, and computer program products determine if a request for an idle bus in a dual bus data processing system is being blocked by one or more pending requests for the other bus. In this circumstance, any such pending request for the other bus is masked by the arbiter so that the request for the idle bus can be granted. Consequently, a more efficient utilization of the dual bus architecture is achieved. In an illustrative embodiment, a bus request is received for a first one of the dual busses. If the address and control busses are unavailable to allow the request to be granted, then an inquiry is made regarding the status of a pending request for the second one of the dual busses that has gained control of the address and control busses. In particular, it is determined whether a primary request has been granted and a secondary request has been pipelined for the second one of the dual busses. If a primary request has been granted and a secondary request has been pipelined, then the priority of the pending requests for the second one of the dual busses are examined. If the priority of the pending requests for the second one of the dual busses are at least as high as the currently pending request for the first one of the dual busses, then these requests are masked so that they no longer appears to be pending, which allows the request for the first one of the dual busses to be granted.

摘要翻译： 方法，仲裁器和计算机程序产品确定对双总线数据处理系统中的空闲总线的请求是否被另一总线的一个或多个未决请求阻止。 在这种情况下，任何这样的对另一总线的等待请求被仲裁器屏蔽，以便可以授予空闲总线的请求。 因此，实现了双总线架构的更有效的利用。 在说明性实施例中，为双总线中的第一个接收总线请求。 如果地址和控制总线不可用于允许请求被授予，则询问已经获得对地址和控制总线的控制的双总线中的第二个的待决请求的状态。 特别地，确定是否已经授权了主要请求，并且为双重总线中的第二个请求已经被流水线化。 如果已经批准了主要请求并且已经流水线地执行了次要请求，则检查双总线中第二个请求的优先级。 如果对于双总线中的第二个双总线的未决请求的优先级至少等于对于双总线中的第一个双总线的当前未决请求，则这些请求被屏蔽，使得它们不再似乎在等待，其中 允许授予第一个双总线的请求。

公开(公告)号：US20120169890A1

公开(公告)日：2012-07-05

申请号：US13156994

申请日：2011-06-09

申请人： YU TIAN ,  Peter Dean SWARTZ

发明人： YU TIAN ,  Peter Dean SWARTZ

IPC分类号： H04N7/32 ,  G06K9/48 ,  H04N5/225

CPC分类号： H04N5/145 ,  H04N19/52 ,  H04N19/527 ,  H04N19/56

摘要： Motion estimation systems and methods are disclosed. An apparatus may include a processing unit to acquire video images and to arrange the video images into a plurality of sequential video frames, and a motion estimation unit that receives the sequential video frames and determines a set of repetitive pattern neighbor candidate vectors for repetitive pattern content in a first frame. The set of repetitive pattern neighbor candidate vectors may be reduced by sorting the set to eliminate spurious repetitive pattern neighbor candidate vectors. The reduced set may be provided to a second adjacent frame. A method may include acquiring a plurality of sequential video frames having a repetitive pattern content, and determining a set of repetitive pattern neighbor candidate vectors for the repetitive pattern content in a first frame of the sequential video frames. The set of repetitive pattern neighbor candidate vectors may be sorted by determining at least one spurious repetitive pattern neighbor candidate vector. The sorted set may be provided to a second adjacent video frame.

摘要翻译： 公开了运动估计系统和方法。 一种装置可以包括：处理单元，用于获取视频图像并将视频图像排列成多个顺序视频帧;以及运动估计单元，其接收顺序视频帧并且确定用于重复模式内容的一组重复模式相邻候选向量 在第一帧。 可以通过对集合进行排序来减少重复模式相邻候选向量的集合，以消除伪重复模式邻居候选向量。 缩小集可以被提供给第二相邻帧。 一种方法可以包括获取具有重复模式内容的多个连续视频帧，以及确定在顺序视频帧的第一帧中重复模式内容的一组重复模式相邻候选向量。 可以通过确定至少一个假重复模式相邻候选向量来对该组重复模式邻居候选向量进行排序。 可以将排序集合提供给第二相邻视频帧。

公开(公告)号：US07223073B2

公开(公告)日：2007-05-29

申请号：US11132527

申请日：2005-05-19

申请人： Peter Dean

发明人： Peter Dean

IPC分类号： B63H1/20

CPC分类号： B63H1/20

摘要： A boat propeller comprising a central hub member and an inner hub assembly that defines a longitudinally extending bore having an inner surface. The exterior surface of the central hub member is sized and shaped for disposition therein the bore of the inner hub assembly in a complementary fashion. In one aspect, the propeller may also comprise a plurality of resilient spacer members positioned such that that the exterior surface of the central hub member is spaced from the inner surface of the bore.

摘要翻译： 一种船用螺旋桨，其包括中心轮毂构件和限定具有内表面的纵向延伸孔的内轮毂组件。 中心毂构件的外表面的尺寸和形状适于以互补的方式配置在内毂组件的孔中。 在一个方面，螺旋桨还可以包括多个弹性间隔件，其定位成使得中心毂构件的外表面与孔的内表面间隔开。

公开(公告)号：USD536744S1

公开(公告)日：2007-02-13

申请号：US29197178

申请日：2004-01-12

申请人： Anatol Wizenberg ,  Peter Dean ,  Wai Bun Choi ,  Ming To Chan ,  Lai Hong Man

设计人： Anatol Wizenberg ,  Peter Dean ,  Wai Bun Choi ,  Ming To Chan ,  Lai Hong Man

公开(公告)号：US06772254B2

公开(公告)日：2004-08-03

申请号：US09855831

申请日：2001-05-15

申请人： Richard Gerard Hofmann ,  Jason Michael Hopp ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

发明人： Richard Gerard Hofmann ,  Jason Michael Hopp ,  Peter Dean LaFauci ,  Dennis Charles Wilkerson

IPC分类号： G06F1314

CPC分类号： G06F13/364

摘要： A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus. Programming apparatus alters the read and write pipeline logic for address pipelining

摘要翻译： 具有重叠的读和写信号与可扩展地址流水线可编程的多主计算机系统在两个重叠的读和写数据总线上独立地增加地址流水线的深度，直到“N”个深度请求。 该系统包括具有地址总线，读总线和写总线的本地总线。 主器件耦合到单独的地址，读取数据和写入数据总线。 从设备通过共享但解耦的地址，读写数据总线连接到数据总线。 仲裁器耦合到数据总线，并允许主机竞争总线所有权。 仲裁器包括读写流水线逻辑，用于处理和优化主数据和从属读写数据总线上的数据传输。 编程设备改变了用于地址流水线化的读写流水线逻辑