公开(公告)号：US20160179715A1

公开(公告)日：2016-06-23

申请号：US14580158

申请日：2014-12-22

申请人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

发明人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

IPC分类号： G06F13/24 ,  G06F13/28

CPC分类号： G06F13/24 ,  G06F13/28 ,  H03F1/3247 ,  Y02D10/14

摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

摘要翻译： 用于将预失真输出样本存储在存储器中的系统包括采样计数器，编程接口模块和比较器。 样本计数器对预失真的输出样本进行计数，生成动态计数值，接收捕获计数器状态信号，并生成第一个计数值。 编程接口模块接收并输出第一计数值，偏移值和捕获控制信号，并产生第一中断信号。 比较器接收第一计数值，偏移值，动态计数值和捕获控制信号，生成最终值，将最终值与动态计数值进行比较，并在最终值等于动态计数值时产生触发信号 基于捕获控制信号的计数值。 触发信号启动将预失真输出样本存储在存储器中。

公开(公告)号：US09231530B1

公开(公告)日：2016-01-05

申请号：US14591928

申请日：2015-01-08

申请人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

发明人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H03F1/32 ,  H04B1/04

CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/24 ,  H03F2200/321 ,  H04B17/13 ,  H04B2001/0425 ,  H04W52/362

摘要： A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal. The processor receives and compares the pre-distorted shaped reference baseband stream data with amplified shaped reference baseband stream data corresponding to the high-power reference RF signal, and adjusts pre-distortion parameters in the pre-distorter module based on the comparison such that the PA generates a linear high-power RF signal.

摘要翻译： 用于校准功率放大器（PA）的系统包括存储器，处理器，数字预失真器（DPD）和数据转换器。 DPD包括编程接口模块，模式发生器，乘法器和预失真器模块。 乘法器将来自存储器的参考基带流数据与由模式发生器产生的模式系数数据相乘以产生形状参考基带流数据。 预失真器模块生成预失真的参考基带流数据。 PA接收与预失真的参考基带流数据相对应的低功率参考射频（RF）信号，并产生高功率参考RF信号。 处理器接收并比较预失真的参考基带流数据与对应于大功率参考RF信号的放大的成形参考基带流数据，并且基于比较调整预失真器模块中的预失真参数，使得 PA产生线性高功率RF信号。

公开(公告)号：US20160054995A1

公开(公告)日：2016-02-25

申请号：US14464134

申请日：2014-08-20

申请人： Leo G. Dehner ,  Jayakrishnan C. Mundarath ,  Peter Z. Rashev

发明人： Leo G. Dehner ,  Jayakrishnan C. Mundarath ,  Peter Z. Rashev

IPC分类号： G06F9/30 ,  G06F17/10

CPC分类号： G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3887 ,  G06F17/10 ,  G06F17/17

摘要： In accordance with at least one embodiment, a processor system is disclosed having a SIMD processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the SIMD processor is a vector processor (VPU) having a plurality of vector Arithmetic Units (AUs) as subsidiary processing elements, and the VPU executes an instruction to transfer table information from a global memory of the VPU to a plurality of local memories accessible by each AU. The VPU also executes an instruction that results in each processing element performing a table lookup from a table stored at its local memory. In response to the instruction, this table lookup uses a portion of a lookup value to access information from the table, and uses another portion of the lookup information to calculate an interpolated resultant based upon the accessed information.

摘要翻译： 根据至少一个实施例，公开了具有SIMD处理器设备的处理器系统，该处理器设备具有被控制以同时处理多个数据的多个辅助处理元件。 根据至少一个实施例，SIMD处理器是具有多个向量算术单元（AU）作为辅助处理单元的向量处理器（VPU），并且VPU执行从VPU的全局存储器传送表信息的指令 到由每个AU访问的多个本地存储器。 VPU还执行一个指令，导致每个处理元素从存储在其本地存储器中的表执行表查找。 响应于该指令，该表查找使用查找值的一部分来访问表中的信息，并且使用查找信息的另一部分基于所访问的信息来计算插值结果。

公开(公告)号：US20140044215A1

公开(公告)日：2014-02-13

申请号：US13569148

申请日：2012-08-07

申请人： Jayakrishnan C. Mundarath ,  Leo G. Dehner ,  Jayesh H. Kotecha ,  Peter Z. Rashev

发明人： Jayakrishnan C. Mundarath ,  Leo G. Dehner ,  Jayesh H. Kotecha ,  Peter Z. Rashev

IPC分类号： H04L25/49

CPC分类号： H04L27/2624

摘要： A method and apparatus for a radio base station (200) generates a multicarrier communication signal having a reduced crest factor by processing a block of samples (231) with a peak search window (271) to identify and suppress signal peaks exceeding a power threshold value.

摘要翻译： 无线电基站（200）的方法和装置通过用峰值搜索窗口（271）处理采样块（231）来产生具有降低波峰因数的多载波通信信号，以识别和抑制超过功率阈值的信号峰值 。

公开(公告)号：US09665510B2

公开(公告)日：2017-05-30

申请号：US14580158

申请日：2014-12-22

申请人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

发明人： Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh ,  Akshat Mittal

IPC分类号： G06F13/24 ,  G06F13/28 ,  H03F1/32 ,  H04B1/04

CPC分类号： G06F13/24 ,  G06F13/28 ,  H03F1/3247 ,  Y02D10/14

摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

公开(公告)号：US10261939B2

公开(公告)日：2019-04-16

申请号：US14464134

申请日：2014-08-20

申请人： Leo G. Dehner ,  Jayakrishnan C. Mundarath ,  Peter Z. Rashev

发明人： Leo G. Dehner ,  Jayakrishnan C. Mundarath ,  Peter Z. Rashev

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F17/10 ,  G06F9/38 ,  H04B1/62 ,  H04L27/36 ,  H03F1/32 ,  H04B1/04

摘要： In accordance with at least one embodiment, a processor system is disclosed having a SIMD processor device that has a plurality of subsidiary processing elements that are controlled to process multiple data concurrently. In accordance with at least one embodiment, the SIMD processor is a vector processor (VPU) having a plurality of vector Arithmetic Units (AUs) as subsidiary processing elements, and the VPU executes an instruction to transfer table information from a global memory of the VPU to a plurality of local memories accessible by each AU. The VPU also executes an instruction that results in each processing element performing a table lookup from a table stored at its local memory. In response to the instruction, this table lookup uses a portion of a lookup value to access information from the table, and uses another portion of the lookup information to calculate an interpolated resultant based upon the accessed information.

公开(公告)号：US20150381216A1

公开(公告)日：2015-12-31

申请号：US14318000

申请日：2014-06-27

申请人： Roi M. Shor ,  Avraham D. Gal ,  Peter Z. Rashev

发明人： Roi M. Shor ,  Avraham D. Gal ,  Peter Z. Rashev

IPC分类号： H04B1/04 ,  H04L25/10

CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H04B2001/0425 ,  H04L25/10

摘要： A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).

摘要翻译： 一种方法和装置用于使用具有多个预失真器单元（301-303）的一个或多个数字预失真块（300）来根据Volterra系列近似模型预失真输入信号样本，每个包括输入乘法级（366-367） 用于将从绝对采样延迟线（362）接收的绝对采样值组合成第一级输出，连接到由第一级输出寻址以产生LUT输出的查找表（368）和多个输出乘法级（ 用于将LUT输出与从幅度采样延迟线（362）和信号采样延迟线（363）接收的样本组合，以产生来自所述预失真器单元的输出信号采样yQ，其中输出信号样本（371-372,373-374） 来自预失真器单元的yQ在输出加法器电路（375）处组合以产生组合信号（yOUT [n]）的一个或多个Volterra项。

公开(公告)号：US09130628B1

公开(公告)日：2015-09-08

申请号：US14582212

申请日：2014-12-24

申请人： Akshat Mittal ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

发明人： Akshat Mittal ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

IPC分类号： H04B1/62 ,  H04B1/04 ,  H04L27/36 ,  H03F1/32

CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/24 ,  H03F3/68 ,  H03F2201/3233 ,  H04B2001/0425 ,  H04L27/368

摘要： A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.

摘要翻译： 用于具有多个天线的RF收发器系统的数字预失真器（DPD）包括DPD控制器，第一和第二地址发生器，流选择和天线选择多路复用器，第一和第二查找表（LUT），第一和第二动态路由逻辑单元 ，乘法器，加法器和累加器。 DPD控制器产生指示天线选择，第一和第二LUT以及输入信号的天线选择，流选择和流选路信号。 DPD控制器通过向天线选择多路复用器提供天线选择信号，将流选择信号提供给流选择多路复用器，并将流路由信号配置为在多个天线之间共享乘法器和第一和第二LUT， 第二动态路由逻辑单元。

公开(公告)号：US09088472B1

公开(公告)日：2015-07-21

申请号：US14591930

申请日：2015-01-08

申请人： Nikhil Jain ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

发明人： Nikhil Jain ,  Arvind Kaushik ,  Peter Z. Rashev ,  Amrit P. Singh

IPC分类号： H04L25/49 ,  H04L27/36 ,  H03F1/32

CPC分类号： H04L27/364 ,  H03F1/3247 ,  H03F3/24 ,  H04L27/368 ,  H04L27/3863

摘要： A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.

摘要翻译： 用于减小同相和正交相位（I / Q）损伤的系统包括用于存储相应的第一，第二，第三和第四值的第一，第二，第三和第四可编程寄存器，第一和第二有限脉冲响应（FIR） 滤波器具有相应的第一和第二组滤波器抽头，以及第一和第二加法器。 第一FIR滤波器接收I输入信号，并且基于I和Q通道的第一和第二值分别产生第一和第二中间输出信号。 第二FIR滤波器接收Q输入信号，并且分别基于I和Q通道的第三和第四值产生第三和第四中间输出信号。 第一和第二加法器分别接收第一和第二以及第三和第四中间输出信号，并产生用于I和Q通道的补偿的I和Q输出信号。

公开(公告)号：US09252821B2

公开(公告)日：2016-02-02

申请号：US14318000

申请日：2014-06-27

申请人： Roi M. Shor ,  Avraham D. Gal ,  Peter Z. Rashev

发明人： Roi M. Shor ,  Avraham D. Gal ,  Peter Z. Rashev

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04B1/04 ,  H04L25/10

CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H04B2001/0425 ,  H04L25/10

摘要： A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).

摘要翻译： 一种方法和装置用于使用具有多个预失真器单元（301-303）的一个或多个数字预失真块（300）来根据Volterra系列近似模型预失真输入信号样本，每个包括输入乘法级（366-367） 用于将从绝对采样延迟线（362）接收的绝对采样值组合成第一级输出，连接到由第一级输出寻址以产生LUT输出的查找表（368）和多个输出乘法级（ 用于将LUT输出与从幅度采样延迟线（362）和信号采样延迟线（363）接收的样本组合，以产生来自所述预失真器单元的输出信号采样yQ，其中输出信号样本（371-372,373-374） 来自预失真器单元的yQ在输出加法器电路（375）处组合以产生组合信号（yOUT [n]）的一个或多个Volterra项。