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公开(公告)号：US09804851B2
公开(公告)日：2017-10-31
申请号：US13064257
申请日：2011-03-14
申请人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
发明人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30112 , G06F9/3861 , G06F21/577 , G06F21/70 , G06F2221/2145
摘要： A data processing system is provided with processing circuitry as well as a bank of 64-bit registers. An instruction decoder decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers. The instruction decoder is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands where all of the operands are 64-bit operands or all of the operands are 32-bit operands. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
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公开(公告)号：US07434007B2
公开(公告)日：2008-10-07
申请号：US11091929
申请日：2005-03-29
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0891
摘要： The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory. When employing exclusive behavior, the n-th level cache memory is operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory. This has been found to reduce the frequency of evictions of lines from the n+1-th level cache memory when employing exclusive behaviour.
摘要翻译： 本发明提供一种用于管理高速缓冲存储器的数据处理装置和方法。 数据处理装置包括用于发出寻求对数据值的访问的访问请求的处理单元和用于存储由处理单元访问的数据值的高速缓存存储器的层级。 高速缓冲存储器的层级包括至少部分地采用彼此排他行为的至少第n级高速缓冲存储器和n + 1级高速缓冲存储器。 每个高速缓冲存储器包括多个高速缓存行，至少一个脏值与每个高速缓存行相关联，并且每个脏值可被设置以指示保持在相关联的高速缓存行中的至少一个数据值更新到比 存储在主存储器中的相应数据值。 当采用独占行为时，在从第n级高速缓冲存储器到第n + 1级高速缓冲存储器的高速缓存行的逐出时，第n级高速缓冲存储器可操作，以附加地通过至少一个 相关联的脏值从第n级高速缓存到第n + 1级缓存。 已经发现，当采用独占行为时，可以减少n + 1级高速缓冲存储器中线路的驱逐频率。
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公开(公告)号：US07587556B2
公开(公告)日：2009-09-08
申请号：US11391689
申请日：2006-03-29
CPC分类号： G06F12/0855 , G06F9/3824 , G06F9/3834 , Y02D10/13
摘要： A store buffer, method and data processing apparatus is disclosed. The store buffer comprises: reception logic operable to receive a request to write a data value to an address in memory; buffer logic having a plurality of entries, each entry being selectively operable to store request information indicative of a previous request and to maintain associated cache information indicating whether a cache line in a cache is currently allocated for writing data values to an address associated with that request; and entry selection logic operable to determine which one of the plurality entries to allocate to store the request using the request information and the associated cache information of the plurality of entries to determine whether a cache line in the cache is currently allocated for writing the data value to the address in memory. By reviewing the entries in the buffer logic and identifying which entry to store the request based on information currently stored by the buffer logic, the need to obtain cache information indicating whether any cache line in a cache is currently allocated for writing the data value may be obviated. In turn, the need to perform a cache look up to obtain the cache information may also be obviated. It will be appreciated that by obviating the need to perform a cache lookup, the power consumption of the store buffer may be reduced. Also, the amount of cache bandwidth consumed by performing unnecessary cache lookups may also be reduced, thereby significantly improving the performance of the cache.
摘要翻译： 公开了存储缓冲器，方法和数据处理装置。 存储缓冲器包括：接收逻辑，用于接收将数据值写入存储器中的地址的请求; 缓冲器逻辑具有多个条目，每个条目可选择性地操作以存储指示先前请求的请求信息，并且维护指示高速缓存中的高速缓存行当前是否被分配用于将数据值写入与该请求相关联的地址的相关联的高速缓存信息 ; 以及条目选择逻辑，其可操作以使用所述多个条目的所述请求信息和所述相关联的高速缓存信息来确定要分配的所述多个条目中的哪一个以存储所述请求，以确定所述高速缓存中的高速缓存行当前是否被分配用于写入所述数据值 到内存中的地址。 通过根据缓冲器逻辑当前存储的信息来查看缓冲器逻辑中的条目并识别存储请求的条目，需要获得指示高速缓存中的任何高速缓存行当前被分配用于写数据值的高速缓存信息可以是 消除了 反过来，也可以避免执行缓存查询以获得高速缓存信息的需要。 应当理解，通过消除执行高速缓存查找的需要，可以减少存储缓冲器的功耗。 此外，还可以减少通过执行不必要的高速缓存查找而消耗的高速缓存带宽的量，从而显着地提高高速缓存的性能。
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4.发明申请Cache logic, data processing apparatus including cache logic, and a method of operating cache logic 有权缓存逻辑，包括高速缓存逻辑的数据处理装置，以及操作高速缓存逻辑的方法公开(公告)号：US20080109606A1
公开(公告)日：2008-05-08
申请号：US11592320
申请日：2006-11-03
IPC分类号： G06F12/08
CPC分类号： G06F12/0859 , G06F12/0804 , G06F12/12
摘要： Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.
摘要翻译： 高速缓存逻辑被提供用于数据处理设备，高速缓存逻辑具有高速缓存存储器，其包括用于存储数据值的多条高速缓存行。 响应于由数据处理装置的设备发出的识别要访问的数据值的存储器地址的访问请求来布置控制逻辑，以执行查找操作以确定该存储器地址的数据值 存储在缓存存储器中。 如果数据值未被存储在高速缓冲存储器中以执行线路填充处理，则该控制逻辑进一步可操作，该线路填充处理包括执行驱逐以驱逐数据处理装置的存储器，以选择高速缓存行的当前内容，保持当前 内容在被驱逐的同时在所选择的高速缓存行中有效，并且从存储器存储到所选择的高速缓存行中，包括访问请求的主题的数据值的新内容。 在发生迁移的同时，控制逻辑允许通过随后的读取访问请求来访问所选择的高速缓存行的当前内容，该读取访问请求尝试读取该当前内容内的数据值，但是阻止所选择的高速缓存行的当前内容被访问 通过随后的写访问请求寻求写入当前内容内的数据值。
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5.发明授权Handling of write access requests to shared memory in a data processing apparatus 有权在数据处理设备中处理对共享存储器的写访问请求公开(公告)号：US08271730B2
公开(公告)日：2012-09-18
申请号：US11907265
申请日：2007-10-10
申请人： Frederic Claude Marie Piry , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugéne Lataille , Stuart David Biles , Richard Roy Grisenthwaite
发明人： Frederic Claude Marie Piry , Philippe Jean-Pierre Raphalen , Norbert Bernard Eugéne Lataille , Stuart David Biles , Richard Roy Grisenthwaite
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A plurality of processing units for performing data processing operations require access to data in shared memory. Each has an associated cache storing a subset of the data for access by that processing unit. A cache coherency protocol ensures data accessed by each unit is up-to-date. Each unit issues a write access request when outputting a data value for storing in shared memory. When the write access request requires both the associated cache and the shared memory to be updated, a coherency operation is initiated within the cache coherency logic. The coherency operation is performed for all of the caches including the cache associated with the processing unit that issued the write access request in order to ensure that the data in those caches is kept coherent.
摘要翻译： 用于执行数据处理操作的多个处理单元需要访问共享存储器中的数据。 每个具有存储用于该处理单元访问的数据的子集的相关联的高速缓存。 缓存一致性协议确保每个单元访问的数据是最新的。 当输出用于存储在共享存储器中的数据值时，每个单元发出写访问请求。 当写访问请求需要更新相关联的高速缓存和共享存储器时，在高速缓存一致性逻辑内启动一致性操作。 对于包括与发出写访问请求的处理单元相关联的缓存的所有缓存执行一致性操作，以便确保这些高速缓存中的数据保持一致。
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公开(公告)号：US20110231633A1
公开(公告)日：2011-09-22
申请号：US13064257
申请日：2011-03-14
申请人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
发明人： Richard Roy Grisenthwaite , David James Seal , Philippe Jean-Pierre Raphalen , Lee Douglas Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/3001 , G06F9/30112 , G06F9/3861 , G06F21/577 , G06F21/70 , G06F2221/2145
摘要： A data processing system 2 is provided with processing circuitry 8, 10, 12 as well as a bank of 64-bit registers 6. An instruction decoder 14 decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers 6. The instruction decoder 14 is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic instruction and logical instruction either all of the operands are 64-bit operands or all of the operands are 32-bit operands. A plurality of exception levels arranged in a hierarchy of exception levels may be supported. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place to that register, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.
摘要翻译： 数据处理系统2设置有处理电路8,10,12以及一组64位寄存器6.指令译码器14解码算术指令和指定算术运算的逻辑指令和对存储在其中的操作数执行的逻辑运算 64位寄存器6.指令解码器14响应于算术指令内的操作数大小字段SF，逻辑指令指定操作数是64位操作数还是32位操作数。 每个64位寄存器存储单个64位操作数或单个32位操作数。 对于给定的算术指令和逻辑指令，所有操作数都是64位操作数，或者所有操作数都是32位操作数。 可以支持以异常级别分层布置的多个异常级别。 如果将交换机设置为较低的异常级别，则检查所使用的寄存器是否先前对该寄存器进行64位写操作。 如果先前对该寄存器进行了这样的64位写操作，则高位32位被刷新，以避免数据从较高异常级别泄漏。
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7.发明授权Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation 有权高速缓存电路，数据处理装置和方法，用于通过选择第一预取行填充操作和第二预取行填充操作之一来预取数据公开(公告)号：US07917701B2
公开(公告)日：2011-03-29
申请号：US11716675
申请日：2007-03-12
申请人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
发明人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request.
摘要翻译： 提供预取电路，其响应于由当前访问请求指定的数据值的存储器地址与预测的存储器地址相同的确定，以执行第一预取行填充操作或第二预取行填充操作以从 记录至少一个另外的数据值，预期该数据值是后续访问请求的主题。 根据当前访问请求的属性执行第一预取行填充操作或第二预取行填充操作的选择。
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8.发明授权Cache logic, data processing apparatus including cache logic, and a method of operating cache logic 有权缓存逻辑，包括高速缓存逻辑的数据处理装置，以及操作高速缓存逻辑的方法公开(公告)号：US07856532B2
公开(公告)日：2010-12-21
申请号：US11592320
申请日：2006-11-03
IPC分类号： G06F13/00
CPC分类号： G06F12/0859 , G06F12/0804 , G06F12/12
摘要： Cache logic is provided for use in a data processing apparatus, the cache logic having a cache storage comprising a plurality of cache lines for storing data values. Control logic is arranged, in response to an access request issued by a device of the data processing apparatus identifying a memory address of the data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. The control logic is further operable if the data value is not stored in the cache storage to perform a linefill process, the linefill process comprising performing an eviction to evict to memory of the data processing apparatus current content of a selected cache line, keeping the current content valid in the selected cache line whilst the eviction is taking place, and storing from the memory into the selected cache line new content including the data value the subject of the access request. Whilst the eviction is taking place, the control logic allows the current content of the selected cache line to be accessed by subsequent read access requests seeking to read a data value within that current content, but prevents the current content of the selected cache line being accessed by subsequent write access requests seeking to write to a data value within that current content.
摘要翻译： 高速缓存逻辑被提供用于数据处理设备，高速缓存逻辑具有高速缓存存储器，其包括用于存储数据值的多条高速缓存行。 响应于由数据处理装置的设备发出的识别要访问的数据值的存储器地址的访问请求来布置控制逻辑，以执行查找操作以确定该存储器地址的数据值 存储在缓存存储器中。 如果数据值未被存储在高速缓冲存储器中以执行线路填充处理，则该控制逻辑进一步可操作，该线路填充处理包括执行驱逐以驱逐数据处理装置的存储器，以选择高速缓存行的当前内容，保持当前 内容在被驱逐的同时在所选择的高速缓存行中有效，并且从存储器存储到所选择的高速缓存行中，包括访问请求的主题的数据值的新内容。 在发生迁移的同时，控制逻辑允许通过随后的读取访问请求来访问所选择的高速缓存行的当前内容，该读取访问请求尝试读取该当前内容内的数据值，但是阻止所选择的高速缓存行的当前内容被访问 通过随后的写访问请求寻求写入当前内容内的数据值。
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公开(公告)号：US20080229070A1
公开(公告)日：2008-09-18
申请号：US11716675
申请日：2007-03-12
申请人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
发明人： Elodie Charra , Philippe Jean-Pierre Raphalen , Frederic Claude Marie Piry , Philippe Luc , Gilles Eric Grandou
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： Cache circuitry, a data processing apparatus including such cache circuitry, and a method for prefetching data into such cache circuitry, are provided. The cache circuitry has a cache storage comprising a plurality of cache lines for storing data values, and control circuitry which is responsive to an access racquet issued by a device of the data processing apparatus identifying a memory address of a data value to be accessed, to cause a lookup operation to be performed to determine whether the data value for that memory address is stored within the cache storage. If not, a linefill operation is initiated to retrieve the data value from memory. Further, prefetch circuitry is provided which is responsive to a determination that the memory address specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch linefill operation to retrieve from memory at least one further data value in anticipation of that data value being the subject of a subsequent access request. The selection of either the first prefetch linefill operation or the second prefetch linefill operation is performed in dependence on an attribute of the current access request. The first prefetch linefill operation involves issuing a sequence of memory addresses to memory, and allocating into a corresponding sequence of cache lines the data values returned from the memory in response to that sequence of addresses. The second prefetch linefill operation comprises issuing a selected memory address to memory, and storing in a linefill buffer the at least one data value returned from the memory in response to that memory address, with that at least one data value only being allocated into the cache when a subsequent access request specifies the selected memory address. By such an approach, the operation of the prefetch circuitry can be altered to take into account the type of access request being issued.
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公开(公告)号：US07761665B2
公开(公告)日：2010-07-20
申请号：US11134513
申请日：2005-05-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/128 , Y02D10/13
摘要： The present invention provides a data processing apparatus and method for handling cache accesses. The data processing apparatus comprises a processing unit operable to issue a series of access requests, each access request having associated therewith an address of a data value to be accessed. Further, the data processing apparatus has an n-way set associative cache memory operable to store data values for access by the processing unit, each way of the cache memory comprising a plurality of cache lines, and each cache line being operable to store a plurality of data values. The cache memory further comprises for each way a TAG storage for storing, for each cache line of that way, a corresponding TAG value. The cache memory is operable, when the processing unit is issuing access requests specifying data values held sequentially in a cache line of a current way of the cache memory, to perform a speculative lookup in at least one TAG storage to determine whether the TAG value associated with the next cache line in one way associated with the at least one TAG storage equals an expected tag value. If that TAG value does equal the expected tag value, and following an access request identifying a last data value in the cache line of the current way, a further access request is issued identifying the next cache line, then the cache memory is operable, without further reference to any TAG storage of the cache memory, to access from that next cache line of the one way the data value the subject of the further access request. This provides significant power savings when handling accesses to a cache memory.
摘要翻译： 本发明提供一种用于处理高速缓存存取的数据处理装置和方法。 数据处理装置包括可操作以发出一系列访问请求的处理单元，每个访问请求具有与其相关联的要访问的数据值的地址。 此外，数据处理装置具有n路组合关联高速缓冲存储器，其可操作以存储用于由处理单元进行访问的数据值，高速缓存存储器的每个方式包括多条高速缓存行，并且每条高速缓存行可操作以存储多个 的数据值。 高速缓冲存储器还包括用于每个方式的TAG存储器，用于针对每个高速缓存行存储相应的TAG值。 高速缓存存储器可操作，当处理单元发出指定在缓冲存储器的当前方式的高速缓存行中顺序保持的数据值的访问请求时，在至少一个TAG存储器中执行推测查找以确定是否相关联的TAG值 其中与所述至少一个TAG存储器相关联的下一个高速缓存行与预期的标签值相等。 如果该TAG值等于预期标签值，并且在当前方式的高速缓存行中识别出最后一个数据值的访问请求之后，则发出另一个访问请求，标识下一个高速缓存行，则高速缓冲存储器可操作，而不需要 进一步参考高速缓冲存储器的任何TAG存储器，从该方式的下一个高速缓存行访问数据值作为进一步访问请求的主题。 当处理对高速缓冲存储器的访问时，这提供了显着的功率节省。
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