公开(公告)号：US06989979B1

公开(公告)日：2006-01-24

申请号：US10605321

申请日：2003-09-22

Applicant: Paul C. F. Tong ,  Wensong Chen ,  Ping Ping Xu ,  Zhiqing Liu

Inventor： Paul C. F. Tong ,  Wensong Chen ,  Ping Ping Xu ,  Zhiqing Liu

IPC: H02H3/20 ,  H02H9/04

CPC classification number: H01L27/0285

Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

Abstract translation: 当发生静电放电（ESD）事件时，VDD至VSS钳位将电流从集成电路芯片内的电源节点分流到接地节点。 电源和地之间串联的电阻和电容在ESD事件发生时在电阻和电容之间的触发节点产生低电压。 由触发器节点驱动的栅极的p沟道晶体管导通，驱动栅极节点。 栅极节点是将ESD电流从电源分流到地的n沟道并联晶体管的栅极。 p沟道反馈晶体管终止ESD分流电流。 p沟道反馈晶体管与电阻并联连接在功率与触发节点之间，栅极节点为栅极。 当发生闩锁触发（例如电子注入）时，由并联的p沟道反馈晶体管阻止电阻器的N阱上的电压降。

公开(公告)号：US06724592B1

公开(公告)日：2004-04-20

申请号：US10248018

申请日：2002-12-11

Applicant: Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu ,  Kwong Shing Lin ,  Anna Tam

Inventor： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu ,  Kwong Shing Lin ,  Anna Tam

IPC: H02H900

CPC classification number: H01L27/0266

Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.

Abstract translation: 针对与源极和漏极上的I / O引脚连接的总线开关晶体管提供引脚对引脚静电放电（ESD）保护。 当施加电力时，p型衬底通常由衬底偏压发生器在地下被泵送。 然而，在引脚到引脚ESD测试期间，电源和接地是浮动的。 通过ESD脉冲通过耦合电容将栅极节点拉高。 栅极节点接通分流晶体管，将ESD脉冲耦合到浮地接地总线。 栅极节点还接通将浮动接地总线连接到浮置基板的短路晶体管。 电阻器将耦合电容器排入衬底，而不是接地。 通过电阻将电流注入衬底。 通过基板触发降低快速恢复电压。

公开(公告)号：US06867957B1

公开(公告)日：2005-03-15

申请号：US10065364

申请日：2002-10-09

Applicant: Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

Inventor： Paul C. F. Tong ,  Ming-Dou Ker ,  Ping Ping Xu

IPC: H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0262 ,  H01L27/0266

Abstract: Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

Abstract translation: 具有非常薄的栅极氧化物的晶体管通过在输出焊盘和接地之间串联两个或更多个晶体管来保护免受氧化物故障。 两个级联晶体管之间的中间源极/漏极节点通常在ESD测试期间浮置，延迟了寄生侧面NPN晶体管的快速恢复导通。 该中间节点用于驱动上触发晶体管的栅极。 下触发晶体管具有通过耦合电容器通过焊盘上的ESD脉冲对其进行充电的栅极节点。 当耦合的ESD脉冲接通触发晶体管时，触发晶体管导通与触发晶体管集成的可控硅整流器（SCR）。

公开(公告)号：US06757147B1

公开(公告)日：2004-06-29

申请号：US10063622

申请日：2002-05-03

Applicant: Paul C. F. Tong ,  David Kwong ,  Ping Ping Xu

Inventor： Paul C. F. Tong ,  David Kwong ,  Ping Ping Xu

IPC: H02H322

CPC classification number: H02H9/046 ,  H01L27/0251

Abstract: A cross-pin electro-static-discharge (ESD) protection device protects against ESD zaps between two I/O pins. Pin A is connected to a drain of a bus-switch transistor and pin B is connected to the transistor's source. An ESD protection device on pin A has an n-channel shunting transistor to an internal ground bus. The gate of the shunting transistor is a cross-gate node that is capacitivly coupled to pin A, and has a leaker resistor to ground. An n-channel cross-grounding transistor has its gate connected to the same cross-gate node, but it connects the internal ground bus to pin B, which is grounded in the pin-to-pin ESD test. An ESD pulse on pin A drives the cross-gate node high, turning on both the shunting transistor and the cross-grounding transistor. The floating internal ground bus is connected to ground by pin B, grounding the substrate of the bus-switch transistor to prevent its turn-on.

Abstract translation: 交叉引脚静电放电（ESD）保护器件可防止两个I / O引脚之间的ESD陷阱。 引脚A连接到总线开关晶体管的漏极，引脚B连接到晶体管的源极。 引脚A上的ESD保护器件具有内部接地总线的n沟道分流晶体管。 分流晶体管的栅极是与栅极A电容耦合的交叉栅极节点，并具有接地的漏电阻。 n沟道交叉接地晶体管的栅极连接到同一个交叉栅极节点，但它将内部接地总线连接到引脚B，引脚B在引脚到引脚ESD测试中接地。 引脚A上的ESD脉冲驱动交叉栅极节点为高电平，导通分流晶体管和交叉接地晶体管。 浮地内部接地总线通过引脚B连接到地，将总线开关晶体管的基板接地，以防止其导通。

公开(公告)号：US06756834B1

公开(公告)日：2004-06-29

申请号：US10249670

申请日：2003-04-29

Applicant: Paul C. F. Tong ,  Siu-Weng Simon Wong ,  Ping Ping Xu ,  Zhi Qing Liu ,  Wensong Chen

Inventor： Paul C. F. Tong ,  Siu-Weng Simon Wong ,  Ping Ping Xu ,  Zhi Qing Liu ,  Wensong Chen

IPC: H03K508

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H03K5/08

Abstract: ESD protection is provided by local ESD-protection devices between each pad and a common-discharge line (CDL). Each ESD-protection device has p-well or p-substrate taps to a local ground rather than to the CDL, reducing noise coupling from the I/O's through the CDL. Another ESD clamp that bypasses the CDL is provided between each pair of internal power and ground buses. Better protection of core circuits during power-to-ground ESD events is provided by bypassing the CDL since only one ESD clamp rather than two ESD-protection devices must turn on. The ESD clamps and ESD-protection devices can be gate-coupled n-channel transistors with coupling capacitors between the pad and the transistor gate. Devices can also be substrate-triggered transistors or active ESD clamps that include an inverter between a coupling capacitor to the CDL and the n-channel transistor gate.

Abstract translation: ESD保护由每个焊盘和公共放电线（CDL）之间的本地ESD保护器件提供。 每个ESD保护装置都具有p-p或p基板抽头到本地而不是CDL，减少了I / O通过CDL的噪声耦合。 在每对内部电源和接地总线之间提供了绕过CDL的另一个ESD钳位。 由于只有一个ESD钳位而不是两个ESD保护器件必须接通，所以通过旁路CDL来提供电源对地静电事件期间核心电路的更好的保护。 ESD钳位和ESD保护器件可以是栅极耦合的n沟道晶体管，其在焊盘和晶体管栅极之间具有耦合电容器。 器件还可以是衬底触发晶体管或有源ESD钳位，其包括在耦合到CDL的耦合电容器与n沟道晶体管栅极之间的反相器。

公开(公告)号：US06965253B1

公开(公告)日：2005-11-15

申请号：US10710298

申请日：2004-06-30

Applicant: Wensong Chen ,  Paul C. F. Tong ,  Ping Ping Xu ,  Zhi Qing Liu

Inventor： Wensong Chen ,  Paul C. F. Tong ,  Ping Ping Xu ,  Zhi Qing Liu

IPC: H03K17/16 ,  H03K19/0175

CPC classification number: H03K17/162

Abstract: A bus switch has reduced input capacitance. Parasitic source-to-well and drain-to-well capacitors are shorted by well-shorting transistors, eliminating these parasitic capacitances. The well-shorting transistors are turned on when the bus-switch transistor is turned on, but are turned off when the bus-switch transistor is turned off and the bus switch isolates signals on its source and drain. The isolated P-well under the bus-switch transistor and the well-shorting transistors is not tied to ground. Instead the isolated P-well is floating when the bus-switch transistor is turned on. When the bus-switch transistor is turned off, the underlying isolated P-well is driven to ground by a biasing transistor in another P-well. Since the isolated P-well has a much lower doping than the N+ source and drain, the capacitance of the well-to-substrate junction is much less than the source-to-well capacitance. Thus input capacitance is reduced, allowing higher frequency switching.

Abstract translation: 总线开关具有降低的输入电容。 寄生源阱和漏 - 阱电容器由短路晶体管短路，消除了这些寄生电容。 当总线开关晶体管导通时，短路晶体管导通，而当总线开关晶体管关断时总线开关晶体管导通，并且总线开关将源极和漏极上的信号隔离。 总线开关晶体管和短路晶体管之间的隔离P阱不接地。 相反，当总线开关晶体管导通时，隔离的P阱是浮置的。 当总线开关晶体管截止时，下一个隔离P阱通过另一个P阱中的偏置晶体管被驱动到地。 由于隔离的P阱具有比N +源极和漏极低得多的掺杂，所以阱到衬底结的电容远小于源极 - 阱电容。 因此，输入电容减小，允许更高频率的切换。