公开(公告)号：US09565036B2

公开(公告)日：2017-02-07

申请号：US13378024

申请日：2010-05-31

Applicant: Jared Zerbe ,  Pradeep Batra ,  Brian Leibowitz

Inventor： Jared Zerbe ,  Pradeep Batra ,  Brian Leibowitz

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H04L25/02 ,  G06F1/10 ,  H03K5/1252

CPC classification number: H04L25/0264 ,  G06F1/10 ,  H03K5/1252

Abstract: A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.

Abstract translation: 第一集成电路（IC）具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。 在其他实施例中，电源电压用于在多个IC上产生时钟信号。

公开(公告)号：US06742097B2

公开(公告)日：2004-05-25

申请号：US09919373

申请日：2001-07-30

Applicant: Steven C. Woo ,  Pradeep Batra

Inventor： Steven C. Woo ,  Pradeep Batra

IPC: G06F1200

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

公开(公告)号：US6122189A

公开(公告)日：2000-09-19

申请号：US165504

申请日：1998-10-02

Applicant: Pradeep Batra

Inventor： Pradeep Batra

IPC: G06F13/16 ,  G11C13/00

CPC classification number: G06F13/16

Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.

Abstract translation: 一种用于将数据存储在存储器中的装置和方法。 掩模信息被嵌入在数据包中，用于指示要存储数据包中的数据值的存储器位置。

公开(公告)号：US07164997B2

公开(公告)日：2007-01-16

申请号：US11233918

申请日：2005-09-23

Applicant: Pradeep Batra ,  Rick A. Rutkowski

Inventor： Pradeep Batra ,  Rick A. Rutkowski

IPC: G06F19/00

CPC classification number: G06F13/4068 ,  G06F13/4072

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract translation: 本文公开了一种用于校准通过改变线路驱动电流产生数据信号的系统中的线路驱动电流并且通过将数据信号与一个或多个参考电压进行比较来解释数据信号的方法和系统。 校准包括改变发射部件处的线路驱动电流。 在不同的线路驱动电流下，接收机参考电压变化，而发送组件向接收组件发送数据。 在每个线路驱动电流下，系统记录不会发生数据错误的最高和最低接收机参考电压。 然后系统检查记录的高和低接收器参考电压以确定期望的线路驱动电流。

公开(公告)号：US20060015275A1

公开(公告)日：2006-01-19

申请号：US11233918

申请日：2005-09-23

Applicant: Pradeep Batra ,  Rick Rutkowski

Inventor： Pradeep Batra ,  Rick Rutkowski

IPC: G01R19/00

CPC classification number: G06F13/4068 ,  G06F13/4072

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

公开(公告)号：US6009487A

公开(公告)日：1999-12-28

申请号：US655830

申请日：1996-05-31

Applicant: Paul Gregory Davis ,  Pradeep Batra ,  John B. Dillon ,  Karnamadakala Krishnamohan ,  James A. Gasbarro

Inventor： Paul Gregory Davis ,  Pradeep Batra ,  John B. Dillon ,  Karnamadakala Krishnamohan ,  James A. Gasbarro

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4072

Abstract: In a system comprising a current controlling device and a plurality of signal lines coupled to the current controlling device, wherein the current controlling device has an output driver including a register, an improved method for setting a current of the output driver for at least one of the plurality of signal lines. The improved method determines a reference register-setting for the register of the current controlling device. The reference register-setting corresponds to a reference voltage for at least one of the plurality of signal lines. A target register-setting is then determined for the register based on the reference register-setting. The target register-setting corresponds to a target voltage for at least one of the plurality of signal lines, wherein the target voltage produces an appropriate swing about the reference voltage. An operational register-setting is then determined for the register based on the target register-setting. The current of the output driver for at least one of the plurality of signal lines is then set based on the operational register-setting so that a swing about the reference voltage is optimal.

Abstract translation: 在包括电流控制装置和耦合到电流控制装置的多条信号线的系统中，其中电流控制装置具有包括寄存器的输出驱动器，用于设置输出驱动器的电流的改进方法， 多条信号线。 改进的方法确定当前控制装置的寄存器的参考寄存器设置。 参考寄存器设置对应于多个信号线中的至少一个信号线的参考电压。 然后根据参考寄存器设置为寄存器确定目标寄存器设置。 目标寄存器设置对应于多个信号线中的至少一个的目标电压，其中目标电压产生关于参考电压的适当的摆幅。 然后根据目标寄存器设置为寄存器确定一个可操作的寄存器设置。 然后基于操作寄存器设置来设置多个信号线中的至少一个的输出驱动器的电流，使得关于参考电压的摆幅是最佳的。

公开(公告)号：US07054771B2

公开(公告)日：2006-05-30

申请号：US11068260

申请日：2005-02-28

Applicant: Pradeep Batra ,  Rick A. Rutkowski

Inventor： Pradeep Batra ,  Rick A. Rutkowski

IPC: G06F19/00

CPC classification number: G06F13/4068 ,  G06F13/4072

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

公开(公告)号：US06954837B2

公开(公告)日：2005-10-11

申请号：US10823115

申请日：2004-04-12

Applicant: Steven C. Woo ,  Pradeep Batra

Inventor： Steven C. Woo ,  Pradeep Batra

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0292 ,  G06F12/023 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.

Abstract translation: 存储器系统包括可以被设置为降低功率模式的物理存储器件或存储器件的等级。 在一个实施例中，硬件存储器控制器根据逻辑地址空间接收存储器指令。 响应于逻辑地址空间内的不同地址的相对使用，存储器控制器以减少所使用的存储器件的数量的方式将逻辑地址空间映射到物理存储器。 然后将其它存储器件设置为降低功率模式。 在另一个实施例中，操作系统维护指示未被分配的物理存储器的部分的空闲页面列表。 操作系统按组定期对该列表进行排序，其中每个组对应于一组或多个存储器件。 这些组按照从接受最重用法的用户顺序排列到接收最轻的用户。 分配内存时，从排序的页面列表中分配内存，以便从已经接收到最高使用率的那些内存设备中优先分配内存。

公开(公告)号：US06546343B1

公开(公告)日：2003-04-08

申请号：US09711606

申请日：2000-11-13

Applicant: Pradeep Batra ,  Rick A. Rutkowski

Inventor： Pradeep Batra ,  Rick A. Rutkowski

IPC: H03B100

CPC classification number: G06F13/4068 ,  G06F13/4072

Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.

Abstract translation: 本文公开了一种用于校准通过改变线路驱动电流产生数据信号的系统中的线路驱动电流并且通过将数据信号与一个或多个参考电压进行比较来解释数据信号的方法和系统。 校准包括改变发射部件处的线路驱动电流。 在不同的线路驱动电流下，接收机参考电压变化，而发送组件向接收组件发送数据。 在每个线路驱动电流下，系统记录不会发生数据错误的最高和最低接收机参考电压。 然后系统检查记录的高和低接收器参考电压以确定期望的线路驱动电流。

公开(公告)号：US6151239A

公开(公告)日：2000-11-21

申请号：US440206

申请日：1999-11-15

Applicant: Pradeep Batra

Inventor： Pradeep Batra

IPC: G06F13/16 ,  G11C13/00

CPC classification number: G06F13/16

Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.