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公开(公告)号：US06742097B2
公开(公告)日：2004-05-25
申请号：US09919373
申请日：2001-07-30
Applicant: Steven C. Woo , Pradeep Batra
Inventor： Steven C. Woo , Pradeep Batra
IPC: G06F1200
CPC classification number: G06F12/0292 , G06F12/023 , G06F2212/1028 , Y02D10/13
Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.
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公开(公告)号：US06954837B2
公开(公告)日：2005-10-11
申请号：US10823115
申请日：2004-04-12
Applicant: Steven C. Woo , Pradeep Batra
Inventor： Steven C. Woo , Pradeep Batra
CPC classification number: G06F12/0292 , G06F12/023 , G06F2212/1028 , Y02D10/13
Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage. When allocating memory, the memory is allocated from the sorted page list so that memory is preferentially allocated from those memory devices that are already receiving the highest usage.
Abstract translation: 存储器系统包括可以被设置为降低功率模式的物理存储器件或存储器件的等级。 在一个实施例中，硬件存储器控制器根据逻辑地址空间接收存储器指令。 响应于逻辑地址空间内的不同地址的相对使用，存储器控制器以减少所使用的存储器件的数量的方式将逻辑地址空间映射到物理存储器。 然后将其它存储器件设置为降低功率模式。 在另一个实施例中，操作系统维护指示未被分配的物理存储器的部分的空闲页面列表。 操作系统按组定期对该列表进行排序，其中每个组对应于一组或多个存储器件。 这些组按照从接受最重用法的用户顺序排列到接收最轻的用户。 分配内存时，从排序的页面列表中分配内存，以便从已经接收到最高使用率的那些内存设备中优先分配内存。
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公开(公告)号：US20120087452A1
公开(公告)日：2012-04-12
申请号：US13378024
申请日：2010-05-31
Applicant: Jared Zerbe , Pradeep Batra , Brian Leibowitz
Inventor： Jared Zerbe , Pradeep Batra , Brian Leibowitz
CPC classification number: H04L25/0264 , G06F1/10 , H03K5/1252
Abstract: A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
Abstract translation: 第一集成电路（IC）具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。 在其他实施例中，电源电压用于在多个IC上产生时钟信号。
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公开(公告)号：US06232796B1
公开(公告)日：2001-05-15
申请号：US09358054
申请日：1999-07-21
Applicant: Pradeep Batra , Stefanos Sidiropoulos
Inventor： Pradeep Batra , Stefanos Sidiropoulos
IPC: H03K1900
CPC classification number: G11C7/1084 , G11C7/1078 , G11C7/1087 , G11C2207/107 , H03K5/08 , H03K5/135
Abstract: A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of said first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.
Abstract translation: 检测以单个时钟边缘发送的两个数据位的方法包括以下步骤：评估第一数据位的值和用单个时钟边沿发送的第二数据位，以产生表示所述第一数据位的值的第一输出位 数据位。 评估步骤可以通过对第一数据位和第二数据位进行积分，或通过识别第一数据位和第二数据位之间的信号转换来实现。 通过简单地传递第二数据位来产生第二个输出位。
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5.发明授权
公开(公告)号：US5249133A
公开(公告)日：1993-09-28
申请号：US684047
申请日：1991-04-10
Applicant: Pradeep Batra
Inventor： Pradeep Batra
IPC: G06F17/50
CPC classification number: G06F17/5022 , G06F17/5081
Abstract: The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.
Abstract translation: 本发明利用了设计的层次性来对可以在布局和逻辑设计之间匹配的块和子块执行分层比较。 因为在比较块的第一次发生时，先前已经验证了内部连接，所以避免了在设计中重复出现多个相同块的冗长比较，并且通过比较与块的输入和输出连接来简单地进行后续的比较。
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Patent Agency Ranking
公开(公告)号：US09565036B2
公开(公告)日：2017-02-07
申请号：US13378024
申请日：2010-05-31
Applicant: Jared Zerbe , Pradeep Batra , Brian Leibowitz
Inventor： Jared Zerbe , Pradeep Batra , Brian Leibowitz
CPC classification number: H04L25/0264 , G06F1/10 , H03K5/1252
Abstract: A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
Abstract translation: 第一集成电路（IC）具有可调延迟电路和第一接口电路。 向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。 第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。 电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。 可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。 在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。 在其他实施例中，电源电压用于在多个IC上产生时钟信号。
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公开(公告)号：US6122189A
公开(公告)日：2000-09-19
申请号：US165504
申请日：1998-10-02
Applicant: Pradeep Batra
Inventor： Pradeep Batra
CPC classification number: G06F13/16
Abstract: An apparatus and method for storing data in a memory. Mask information is embedded in a data packet and used to indicate memory locations at which data values in the data packet are to be stored.
Abstract translation: 一种用于将数据存储在存储器中的装置和方法。 掩模信息被嵌入在数据包中，用于指示要存储数据包中的数据值的存储器位置。
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公开(公告)号：US06988044B2
公开(公告)日：2006-01-17
申请号：US10409033
申请日：2003-04-08
Applicant: Pradeep Batra , Rick A. Rutkowski
Inventor： Pradeep Batra , Rick A. Rutkowski
IPC: G06R19/00
CPC classification number: G06F13/4068 , G06F13/4072
Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.
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公开(公告)号：US20050146963A1
公开(公告)日：2005-07-07
申请号：US11068260
申请日：2005-02-28
Applicant: Pradeep Batra , Rick Rutkowski
Inventor： Pradeep Batra , Rick Rutkowski
CPC classification number: G06F13/4068 , G06F13/4072
Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.
Abstract translation: 本文公开了一种用于校准通过改变线路驱动电流产生数据信号的系统中的线路驱动电流并且通过将数据信号与一个或多个参考电压进行比较来解释数据信号的方法和系统。 校准包括改变发射部件处的线路驱动电流。 在不同的线路驱动电流下，接收机参考电压变化，而发送组件向接收组件发送数据。 在每个线路驱动电流下，系统记录不会发生数据错误的最高和最低接收机参考电压。 然后系统检查记录的高和低接收器参考电压以确定期望的线路驱动电流。
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公开(公告)号：US07164997B2
公开(公告)日：2007-01-16
申请号：US11233918
申请日：2005-09-23
Applicant: Pradeep Batra , Rick A. Rutkowski
Inventor： Pradeep Batra , Rick A. Rutkowski
IPC: G06F19/00
CPC classification number: G06F13/4068 , G06F13/4072
Abstract: Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing them to one or more reference voltages. The calibration includes varying the line drive current at a transmitting component. At different line drive currents, a receiver reference voltage is varied while the transmitting component transmits data to a receiving component. At each line drive current, the system records the highest and lowest receiver reference voltages at which data errors do not occur. The system then examines the recorded high and low receiver reference voltages to determine a desirable line drive current.
Abstract translation: 本文公开了一种用于校准通过改变线路驱动电流产生数据信号的系统中的线路驱动电流并且通过将数据信号与一个或多个参考电压进行比较来解释数据信号的方法和系统。 校准包括改变发射部件处的线路驱动电流。 在不同的线路驱动电流下，接收机参考电压变化，而发送组件向接收组件发送数据。 在每个线路驱动电流下，系统记录不会发生数据错误的最高和最低接收机参考电压。 然后系统检查记录的高和低接收器参考电压以确定期望的线路驱动电流。
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