公开(公告)号：US06268755B1

公开(公告)日：2001-07-31

申请号：US08963836

申请日：1997-11-04

Applicant: R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

Inventor： R. Travis Summerlin ,  Joseph A. Devore ,  William E. Grose

IPC: H03K190185

CPC classification number: H03K19/018585 ,  H03K19/00361

Abstract: A voltage level shifting circuit (60) and method for accomplishing a voltage level change includes a voltage level shifting circuit (65) to change an input voltage to a shifted voltage level. A second stage (67) is connected between a voltage source at the shifted voltage level (68) and the reference potential. The second stage (67) includes active devices (66,82) that are controlled by the voltage level shifting circuit (65). The second stage (67) also includes slope resistors (86,88) connected in series between the active devices (66,82) of the second stage (67).

Abstract translation: 电压电平移动电路（60）和用于实现电压电平变化的方法包括将输入电压改变到移位的电压电平的电压电平移位电路（65）。 第二级（67）连接在变换的电压电平（68）的电压源和参考电位之间。 第二级（67）包括由电压电平移位电路（65）控制的有源器件（66,82）。 第二级（67）还包括串联连接在第二级（67）的有源器件（66,82）之间的斜率电阻器（86,88）。

公开(公告)号：US06236098B1

公开(公告)日：2001-05-22

申请号：US09061452

申请日：1998-04-16

Applicant: Taylor R. Efland ,  R. Travis Summerlin ,  Joseph A. Devore

Inventor： Taylor R. Efland ,  R. Travis Summerlin ,  Joseph A. Devore

IPC: H01L31058

CPC classification number: H01L23/34 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2924/3011

Abstract: An integrated circuit chip (10, 50, 100) may comprise an integrated circuit (14, 54, 108, 110, 112) formed in a semiconductor layer (12, 52, 102). A thermal contact (16, 56, 116) may be formed at a high temperature region of the integrated circuit (14, 54, 108, 110, 112). A thick plated metal layer (40, 80, 140) may be generally isolated from the integrated circuit (14, 54, 108, 110, 112). The thick plated metal layer (40, 80, 140) may include a base (42, 82, 142) and an exposed surface (44, 84, 144) opposite the base (42, 82, 142). The base (42, 82, 142) may be coupled to the thermal contact (16, 56, 116) to receive thermal energy of the high temperature region. The exposed surface (44, 84, 144) may dissipate thermal energy received by the thick plated metal layer (40, 80, 140).

Abstract translation: 集成电路芯片（10,50,100）可以包括形成在半导体层（12,52,102）中的集成电路（14,54,108,110,112）。 可以在集成电路（14,54,108,110,112）的高温区域形成热接触（16,56,116）。 厚电镀金属层（40,80,140）可以通常与集成电路（14,54,108,110,112）隔离。 厚电镀金属层（40,80,140）可以包括基部（42,82,142）和与基部（42,82,142）相对的暴露表面（44,84,144）。 基座（42,82,142）可以联接到热接触件（16,56,116）以接收高温区域的热能。 暴露表面（44,84,144）可以消散由厚镀金属层（40,80,140）接收的热能。