公开(公告)号：US20240282726A1

公开(公告)日：2024-08-22

申请号：US18170581

申请日：2023-02-17

申请人： NXP USA, INC.

发明人： Trent Uehling

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2924/04953

摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a conductive probe plug on an exposed portion of a die pad of a semiconductor die by way of an electroless plating process. A top surface of the conductive probe plug extends above a top surface of a top passivation layer of the semiconductor die. A copper pillar is formed over the conductive probe plug by way of an electrolytic plating process. Outer sidewalls of the copper pillar surround the top surface of the conductive probe plug. A top surface of the copper pillar is plated with a solder plate material and reflowed to form a solder cap on the top of the copper pillar.

公开(公告)号：US11999001B2

公开(公告)日：2024-06-04

申请号：US17545322

申请日：2021-12-08

申请人： Adeia Semiconductor Technologies LLC

发明人： Cyprian Emeka Uzoh

IPC分类号： H05K1/11 ,  B23K20/00 ,  B23K20/02 ,  H01L21/50 ,  H01L23/00 ,  H01L23/10 ,  H01L23/48 ,  H01L23/49 ,  H01L23/498 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K13/04 ,  H01L21/48 ,  H01L21/768

CPC分类号： B23K20/023 ,  B23K20/002 ,  H01L21/50 ,  H01L23/10 ,  H01L23/481 ,  H01L23/49 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H05K1/11 ,  H05K1/14 ,  H05K1/144 ,  H05K1/18 ,  H05K3/0094 ,  H05K3/34 ,  H05K13/046 ,  H05K13/0465 ,  H01L21/4853 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/27 ,  H01L2224/02372 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05138 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/16501 ,  H01L2224/16503 ,  H01L2224/16505 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/27462 ,  H01L2224/27464 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29138 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81075 ,  H01L2224/8112 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81825 ,  H01L2224/83075 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83825 ,  H01L2924/00014 ,  H01L2924/381 ,  H05K1/111 ,  H05K2201/04 ,  H05K2203/04 ,  H01L2224/8112 ,  H01L2924/00014 ,  H01L2224/1147 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04953 ,  H01L2224/0518 ,  H01L2924/01071 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05181 ,  H01L2924/00014 ,  H01L2224/05171 ,  H01L2924/01042 ,  H01L2224/05138 ,  H01L2924/01015 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/05187 ,  H01L2924/04941 ,  H01L2224/05155 ,  H01L2924/01015 ,  H01L2224/05157 ,  H01L2924/01015 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/05155 ,  H01L2924/01074 ,  H01L2224/13105 ,  H01L2924/01047 ,  H01L2224/13109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/13138 ,  H01L2924/01034 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11452 ,  H01L2924/00014 ,  H01L2224/16501 ,  H01L2924/00012 ,  H01L2224/16505 ,  H01L2924/00012 ,  H01L2224/14131 ,  H01L2924/00014 ,  H01L2224/05026 ,  H01L2924/00012 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13184 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2224/73203 ,  H01L2924/00012 ,  H01L2224/27462 ,  H01L2924/00014 ,  H01L2224/27464 ,  H01L2924/00014 ,  H01L2224/2745 ,  H01L2924/00014 ,  H01L2224/27452 ,  H01L2924/00014 ,  H01L2224/29105 ,  H01L2924/01047 ,  H01L2224/29109 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2224/29138 ,  H01L2924/01034 ,  H01L2224/32501 ,  H01L2924/00012 ,  H01L2224/32505 ,  H01L2924/00012 ,  H01L2224/8312 ,  H01L2924/00014 ,  H01L2224/1319 ,  H01L2924/07025 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/13018 ,  H01L2924/00012

摘要： A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

公开(公告)号：US20240120298A1

公开(公告)日：2024-04-11

申请号：US17962131

申请日：2022-10-07

申请人： Infineon Technologies AG

发明人： Dietrich Bonart ,  Bernhard Weidgans

IPC分类号： H01L23/00 ,  H01L23/544

CPC分类号： H01L24/05 ,  H01L23/544 ,  H01L24/03 ,  H01L24/06 ,  H01L2224/03001 ,  H01L2224/0346 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05551 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05566 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06515 ,  H01L2924/01014 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/04941

摘要： A semiconductor die includes: a semiconductor substrate; a first contact pad structure above the semiconductor substrate, the first contact pad structure including a metal contact pad configured for electrical contact and a metal layer adjoining an underside of the metal contact pad and jutting out beyond an edge of the metal contact pad; and a first optical detection marker in a periphery of the first contact pad structure and having a different contrast than the metal contact pad. The first optical detection marker includes a region of the metal layer that is adjacent to the edge of the metal contact pad and unobstructed by the metal contact pad so as to be optically visible in a plan view of the semiconductor die. A method of producing the semiconductor die is also described.

公开(公告)号：US20240038753A1

公开(公告)日：2024-02-01

申请号：US17816502

申请日：2022-08-01

申请人： QUALCOMM Incorporated

发明人： Aniket Patil ,  Hong Bok We ,  Joan Rey Villarba Buot

IPC分类号： H01L27/01 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L27/01 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/03 ,  H01L23/5383 ,  H01L25/0652 ,  H01L24/04 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05073 ,  H01L2224/0231 ,  H01L2224/039 ,  H01L2224/05573 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/06138 ,  H01L24/16 ,  H01L2224/16225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/32 ,  H01L2224/32225 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L24/92 ,  H01L2224/92125

摘要： Deep trench capacitors (DTCs) employing bypass metal trace signal routing supporting signal bypass routing, and related integrated circuit (IC) packages and fabrication methods are disclosed. The DTC includes an outer metallization layer (e.g., a redistribution layer (RDL)) to provide an external interface to the DTC. In exemplary aspects, to make available signal routes that can extend through a DTC, an outer metallization layer of the DTC includes additional metal interconnects. These additional metal interconnects are not coupled the capacitors in the DTC. These additional metal interconnects are interconnected to each other by metal traces (e.g., metal lines) in the outer metallization layer of the DTC to provide bypass signal routes through the DTC. This is opposed to signal paths in a package substrate in which the DTC is coupled or embedded having to be routed around the DTC in the package substrate.

公开(公告)号：US11791286B2

公开(公告)日：2023-10-17

申请号：US17405487

申请日：2021-08-18

申请人： Samsung Electronics Co., Ltd.

发明人： Youn-ji Min ,  Seok-hyun Lee

IPC分类号： H01L23/00

CPC分类号： H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05556 ,  H01L2924/00012 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/11464 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014

摘要： Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance.

公开(公告)号：US20230238400A1

公开(公告)日：2023-07-27

申请号：US17901613

申请日：2022-09-01

申请人： Samsung Display Co., LTD.

发明人： Seung Lyong BOK ,  Hyun Joon KIM

IPC分类号： H01L27/12 ,  H01L25/16 ,  H01L23/00 ,  G06F3/041 ,  G06F3/044

CPC分类号： H01L27/1248 ,  H01L25/167 ,  H01L24/05 ,  H01L27/124 ,  G06F3/0412 ,  G06F3/0446 ,  G06F3/04184 ,  H01L24/08 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05562 ,  H01L2224/05686 ,  H01L2224/08145 ,  H01L2224/05566 ,  H01L2224/05567 ,  H01L2924/0549 ,  H01L24/16 ,  H01L2224/16145

摘要： Provided are a display device and a tiled display device. The display device according to one or more embodiments includes a substrate, transistors above the substrate, a first organic insulating layer above the transistors, a first connection electrode above the first organic insulating layer, and electrically connected to at least one of the transistors, a second connection electrode above the first organic insulating layer, a first power supply line configured to receive a first power voltage, above the first organic insulating layer, and connected to the second connection electrode, and a second organic insulating layer above the first power supply line, and defining an opening area exposing the first power supply line.

公开(公告)号：US11664297B2

公开(公告)日：2023-05-30

申请号：US17398086

申请日：2021-08-10

申请人： LBSEMICON CO., LTD.

发明人： Jae Jin Kwon

IPC分类号： H01L23/488 ,  H01L23/00

CPC分类号： H01L23/488 ,  H01L23/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13147 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

摘要： Provided is a method of manufacturing a semiconductor package, the method including a first step for forming a primary solder ball on an under bump metallurgy (UBM) structure, and a second step for forming a secondary solder ball on an upper surface of the UBM structure by performing a reflow process on the primary solder ball while a side wall of the UBM structure is exposed.

公开(公告)号：US20190074255A1

公开(公告)日：2019-03-07

申请号：US16181130

申请日：2018-11-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei CHEN ,  Hao-Yi TSAI ,  Mirng-Ji LII ,  Chen-Hua YU

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

公开(公告)号：US20180301429A1

公开(公告)日：2018-10-18

申请号：US16018128

申请日：2018-06-26

申请人： Rohm Co., Ltd.

发明人： Tadahiro Morifuji ,  Shigeyuki Ueda

IPC分类号： H01L23/00 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05027 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05561 ,  H01L2224/05583 ,  H01L2224/0569 ,  H01L2224/10122 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/1356 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metal layer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

公开(公告)号：US20170338188A1

公开(公告)日：2017-11-23

申请号：US15477717

申请日：2017-04-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei CHEN ,  Hao-Yi TSAI ,  Mirng-Ji LII ,  Chen-Hua YU

IPC分类号： H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L23/525

CPC分类号： H01L23/562 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/522 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.