利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.02 秒)

    Data streamer
    1.
    发明授权
    Data streamer 有权
    数据流

    公开(公告)号：US07548996B2

    公开(公告)日：2009-06-16

    申请号：US11224738

    申请日：2005-09-12

    申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  John Poole, legal representative ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    发明人： David Poole

    IPC分类号： G06F13/28

    CPC分类号： G06F13/30 ,  G06F13/1605

    摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    DEBUG INFORMATION COLLECTION METHOD AND DEBUG INFORMATION COLLECTION SYSTEM
    2.
    发明申请
    DEBUG INFORMATION COLLECTION METHOD AND DEBUG INFORMATION COLLECTION SYSTEM 审中-公开
    调试信息采集方法和调试信息采集系统

    公开(公告)号：US20080141224A1

    公开(公告)日：2008-06-12

    申请号：US11947221

    申请日：2007-11-29

    申请人： Shinichiro Kawasaki ,  Toru Nojiri

    发明人： Shinichiro Kawasaki ,  Toru Nojiri

    IPC分类号： G06F11/36

    CPC分类号： G06F11/362

    摘要： In a software distribution unit, a binary-code analysis unit determines a total set of insertion positions at which probes can be inserted into software. A binary-code change unit determines the population of insertion positions of probes to be inserted into the software and the number of insertion positions of probes to be inserted on a device basis. Then, the binary-code change unit selects, from the population, insertion positions of probes as many as the determined number of insertion positions and inserts the probes into the software at the selected insertion positions. A software distribution unit distributes, to the device, the software into which the probes are inserted. As a result, it is possible to reduce both a load on the device side and a load on the software developer side at the same time and to acquire uniform debug information without deviations.

    摘要翻译： 在软件分发单元中，二进制代码分析单元确定可以将探针插入到软件中的插入位置的总组。 二进制代码改变单元确定要插入到软件中的探针的插入位置的数量和要在设备基础上插入的探针的插入位置的数量。 然后，二进制代码改变单元从群体中选择探测器的插入位置与所确定的插入位置数量一样多，并将探针插入到所选插入位置的软件中。 软件分发单元向设备分发插入探针的软件。 结果，可以同时减少设备侧的负载和软件开发者侧的负载，并且可以在没有偏差的情况下获取统一的调试信息。

    DATA PROCESSOR
    3.
    发明申请
    DATA PROCESSOR 有权
    数据处理器

    公开(公告)号：US20080086729A1

    公开(公告)日：2008-04-10

    申请号：US11869565

    申请日：2007-10-09

    申请人： Yuki Kondoh ,  Takashi Matsumoto ,  Keisuke Toyama ,  Toru Nojiri

    发明人： Yuki Kondoh ,  Takashi Matsumoto ,  Keisuke Toyama ,  Toru Nojiri

    IPC分类号： G06F9/455 ,  G06F9/50

    CPC分类号： G06F9/5077 ,  G06F9/45558 ,  G06F2009/45583

    摘要： A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (101), each running an application program under controls of different operating systems, and a virtual machine manager (190) for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (140, 150, 151); and a resource access management module (110) for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.

    摘要翻译： 数据处理器包括：中央处理单元（CPU），其中在不同操作系统的控制下运行应用程序的多个虚拟机（101）和用于控制多个虚拟机的虚拟机器管理器（190） 根据在模式寄存器（140,150,151）中设置的信息来选择性地布置机器; 以及用于管理对可用于所述多个虚拟机的硬件资源的访问的资源访问管理模块（110）。 资源访问管理模块将在模式寄存器中设置的信息和中央处理单元的访问控制信息作为输入接受到硬件资源，将由此输入的信息与设置在控制寄存器中的信息进行比较，并且控制是否 响应于访问控制信息允许访问硬件资源。 因此，可以减少涉及系统规格变化的重新设计，并且可以防止由于资源争用引起的故障。 本发明有助于提高安全性。

    Data streamer
    4.
    发明授权
    Data streamer 有权
    数据流

    公开(公告)号：US06434649B1

    公开(公告)日：2002-08-13

    申请号：US09173297

    申请日：1998-10-14

    申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    发明人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    IPC分类号： G06F1300

    CPC分类号： G06F13/30 ,  G06F13/1605

    摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息 的模块，包括内存和I / O设备。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    Program failure analysis system, failure analysis method, and emulator device
    7.
    发明授权
    Program failure analysis system, failure analysis method, and emulator device 失效
    程序故障分析系统，故障分析方法和仿真器

    公开(公告)号：US07818620B2

    公开(公告)日：2010-10-19

    申请号：US11832040

    申请日：2007-08-01

    申请人： Takehiko Nagano ,  Toru Nojiri ,  Tomohiko Shigeoka

    发明人： Takehiko Nagano ,  Toru Nojiri ,  Tomohiko Shigeoka

    IPC分类号： G06F11/00

    CPC分类号： G06F11/261 ,  G06F11/3652

    摘要： A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced stop signal between an ICE device and the CPU is considered and set, and a CPU forced stop signal issuance position which is prior to a stop target position is determined. Based on a real-time tracing function of the CPU, at an issuance position and timing of the CPU forced stop signal on the execution of the program, the CPU forced stop signal is issued, the CPU is stopped, and the event is acquired. By this means, an arbitrary number of events of the program can be acquired regardless of the number of breakpoint registers.

    摘要翻译： CPU强制停止信号被用作由目标系统的CPU停止在ROM上执行的程序的执行的装置。 考虑并设置在ICE装置和CPU之间停止CPU发出CPU强制停止信号所需的时间，并确定停止目标位置之前的CPU强制停止信号发出位置。 基于CPU的实时跟踪功能，在执行程序时CPU强制停止信号的发行位​​置和定时，发出CPU强制停止信号，CPU停止，并获取事件。 通过这种方式，可以获取程序的任意数量的事件，而不管断点寄存器的数量。

    Computer system obtaining information on capacity and usage of an area used by a computer and notifying the computer the status thereof
    10.
    发明授权
    Computer system obtaining information on capacity and usage of an area used by a computer and notifying the computer the status thereof 有权
    计算机系统获取计算机使用的区域的容量和使用信息，并通知计算机的状态

    公开(公告)号：US07103733B2

    公开(公告)日：2006-09-05

    申请号：US10302153

    申请日：2002-11-21

    申请人： Masayasu Asano ,  Yasunori Kaneda ,  Toru Nojiri

    发明人： Masayasu Asano ,  Yasunori Kaneda ,  Toru Nojiri

    IPC分类号： G06F12/00

    CPC分类号： G06F11/3442 ,  G06F3/0605 ,  G06F3/0653 ,  G06F11/3433 ,  G06F11/3485 ,  G06F2206/1012

    摘要： A computer system includes a plurality of computers and at least one storage connected to the plurality of computers. The storage includes a device that obtains information concerning areas within the storage that are used by the respective plurality of computers, a device that obtains information concerning a capacity within each of the areas that is used by each of the plurality of computers to store-data, and a device that notifies at least one of the plurality of computers of a status of the areas within the at least one storage. The computer system utilizes and manage the storage, without having each of the computers utilize and manage the storages with regard to storage capacity.

    摘要翻译： 计算机系统包括多个计算机和连接到多个计算机的至少一个存储器。 所述存储装置包括：获取关于所述存储器中由所述各个计算机使用的区域的信息的装置;获取与所述多个计算机中的每一个使用的每个所述区域内的容量相关的存储数据的信息的装置 以及将所述多个计算机中的至少一个通知所述至少一个存储器内的区域的状态的设备。 计算机系统利用和管理存储器，而不必使每个计算机利用和管理关于存储容量的存储器。