公开(公告)号：US5905999A

公开(公告)日：1999-05-18

申请号：US638661

申请日：1996-04-29

申请人： Peichun Peter Liu ,  Salim Ahmed Shah ,  Rajinder Paul Singh

发明人： Peichun Peter Liu ,  Salim Ahmed Shah ,  Rajinder Paul Singh

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0851

摘要： A cache sub-array arbitration circuit for receiving a plurality of address operands from a pending line of processor instructions in order to pre-fetch data needed in any memory access request in the pending instructions. The sub-array arbitration circuit compares at least two addresses corresponding to memory locations in the cache, and determines in which sub-arrays the memory locations reside. If the two memory locations reside in the same sub-array, the arbitration circuit sends the higher priority address to the sub-array. If a received address operand is the real address of a cache miss, the arbitration circuit sends the cache miss address to the sub-array before other pre-fetch memory access request.

摘要翻译： 一种高速缓存子阵列仲裁电路，用于从未决的处理器指令行接收多个地址操作数，以便预取在未决指令中的任何存储器访问请求中所需的数据。 子阵列仲裁电路将至少两个对应于高速缓存中的存储器位置的地址进行比较，并确定存储器位置在哪个子阵列中。 如果两个存储器位置位于相同的子阵列中，则仲裁电路将较高优先级地址发送到子阵列。 如果接收到的地址操作数是高速缓存未命中的真实地址，则仲裁电路在其他预取存储器访问请求之前将高速缓存未命中地址发送到子阵列。

公开(公告)号：US5937429A

公开(公告)日：1999-08-10

申请号：US844550

申请日：1997-04-21

申请人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

发明人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

IPC分类号： G06F12/12

CPC分类号： G06F12/127

摘要： A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

摘要翻译： 描述了具有可选择的高速缓存线更换方案的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器具有多个高速缓存线，多个令牌寄存器，令牌和选择电路。 令牌寄存器以环形配置相互连接。 存在相等数量的令牌寄存器和高速缓存行，并且每个令牌寄存器与其中一个高速缓存行相关联。 令牌被用于将一个缓存行指示为由令牌结算的相关联的令牌寄存器替换的候选。 选择电路与所有令牌寄存器相关联。 该选择电路提供至少两种方法来控制令牌在令牌寄存器的环内的移动，以便在运行时期间可选择。 令牌移动的每种方法代表高速缓存行替换方案。

公开(公告)号：US5787478A

公开(公告)日：1998-07-28

申请号：US810775

申请日：1997-03-05

申请人： Dwain Alan Hicks ,  Peichun Peter Liu ,  Michael John Mayfield ,  Rajinder Paul Singh

发明人： Dwain Alan Hicks ,  Peichun Peter Liu ,  Michael John Mayfield ,  Rajinder Paul Singh

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811

摘要： A method and system of implementing a cache coherency mechanism for supporting a non-inclusive cache memory hierarchy within a data processing system is disclosed. In accordance with the method and system of the invention, the memory hierarchy includes a primary cache memory, a secondary cache memory, and a main memory. The primary cache memory and the secondary cache memory are non-inclusive. Further, a first state bit and a second state bit are provided within the primary cache, in association with each cache line of the primary cache. As a preferred embodiment, the first state bit is set only if a corresponding cache line in the primary cache memory has been modified under a write-through mode, while the second state bit is set only if a corresponding cache line also exists in the secondary cache memory. As such, the cache coherency between the primary cache memory and the secondary cache memory can be maintained by utilizing the first state bit and the second state bit in the primary cache memory.

摘要翻译： 公开了一种实现用于在数据处理系统内支持非包容性高速缓存存储器层级的高速缓存一致性机制的方法和系统。 根据本发明的方法和系统，存储器层级包括主高速缓冲存储器，副高速缓冲存储器和主存储器。 主缓冲存储器和次高速缓冲存储器是不包含的。 此外，与主缓存器的每个高速缓存行相关联地，在主缓存器内提供第一状态位和第二状态位。 作为优选实施例，仅当在一级高速缓冲存储器中的对应的高速缓存行已经在直写模式下被修改时才设置第一状态位，而仅当相应的高速缓存行也存在于次级 高速缓存存储器。 这样，可以通过利用主高速缓存存储器中的第一状态位和第二状态位来维持主高速缓存存储器和辅助高速缓冲存储器之间的高速缓存一致性。

公开(公告)号：US6041390A

公开(公告)日：2000-03-21

申请号：US773545

申请日：1996-12-23

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F12/12

CPC分类号： G06F12/121

摘要： A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.

摘要翻译： 公开了一种用于具有冗余高速缓存行的高速缓冲存储器内的高速缓存行替换机制。 根据本发明的优选实施例，该机制包括令牌，多个令牌寄存器，多个分配指示电路，多个旁路电路，以及用于响应于位置替换高速缓冲存储器内的高速缓存行的电路 的令牌。 顺便提及，该令牌用于指示用于高速缓存行替换的候选高速缓存行。 令牌寄存器以环形配置连接，并且每个令牌寄存器与高速缓冲存储器的高速缓存行相关联，包括所有冗余高速缓存行。 通常，这些令牌寄存器之一包含令牌。 每个令牌寄存器具有分配指示电路。 分配指示电路用于指示与分配指示电路相关联的高速缓存行是否正在进行分配过程。 每个令牌寄存器还具有旁路电路。 响应于来自相关联的分配指示电路的指示，利用旁路电路将令牌从一个令牌寄存器传送到相邻令牌电路。

公开(公告)号：US5802567A

公开(公告)日：1998-09-01

申请号：US742233

申请日：1996-10-31

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/1054 ,  G06F12/0864

摘要： A cache memory having a mechanism for managing offset and aliasing conditions is disclosed. In accordance with a preferred embodiment of the invention, the cache memory comprises a first directory circuit, a second directory circuit, a multiple number of most recently used bits, and a multiple number of set/reset circuits. The first directory circuit, having multiple caches lines, is utilized to receive partial effective addresses. The second directory circuit is utilized to receive an output from the first directory circuit. A most recently used bit is associated with each cache line within the first directory circuit. The set/reset circuit, coupled to each of the most recently used bits, is utilized to set one of the most recently used bits to a first state while concurrently resetting the rest of the most recently used bits to a second state within a single cycle during an occurrence of an offset or aliasing conditions such that offset or aliasing conditions can be more efficiently managed.

摘要翻译： 公开了一种具有用于管理偏移和混叠条件的机制的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器包括第一目录电路，第二目录电路，多个最近使用的位以及多个设置/复位电路。 具有多个高速缓存行的第一目录电路被用于接收部分有效地址。 第二目录电路用于接收来自第一目录电路的输出。 最近使用的位与第一目录电路内的每个高速缓存行相关联。 耦合到每个最近使用的位的置位/复位电路用于将最近使用的位之一设置为第一状态，同时将单个周期内的最近使用的位的其余部分复位到第二状态 在偏移或混叠条件的发生期间，可以更有效地管理偏移或混叠条件。

公开(公告)号：US5761714A

公开(公告)日：1998-06-02

申请号：US638263

申请日：1996-04-26

申请人： Peichun Peter Liu ,  Rajinder Paul Singh

发明人： Peichun Peter Liu ,  Rajinder Paul Singh

IPC分类号： G06F12/06 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0851

摘要： An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.

摘要翻译： 公开了一种具有单周期多路访问能力的交错缓存。 交错缓存存储器包括存储单元的多个子阵列，用于接收这些子阵列的多个输入地址的仲裁逻辑电路，以及用于将这些多个输入地址应用于这些子阵列的地址输入电路。 这些子阵列中的每一个包括偶数数据部分和奇数数据部分和三个内容可寻址存储器，用于接收多个输入地址以便与存储在这三个可内容寻址存储器中的标签进行比较。 三个可内容寻址存储器中的第一个与偶数据部分相关联，并且三个可内容寻址存储器中的第二个与奇数据部分相关联。 如果多个输入地址尝试访问相同子阵列的相同数据段，则仲裁逻辑电路然后用于选择多个输入地址中的一个进行进行。

公开(公告)号：US06304939B1

公开(公告)日：2001-10-16

申请号：US09404036

申请日：1999-09-23

申请人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

发明人： Peichun Peter Liu ,  Rajinder Paul Singh ,  Shih-Hsiung Steve Tung

IPC分类号： G06F1212

CPC分类号： G06F12/121

摘要： A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.

摘要翻译： 公开了一种用于具有冗余高速缓存线的高速缓冲存储器内的高速缓存行替换的机制。 根据本发明的优选实施例，该机制包括令牌，多个令牌寄存器，多个分配指示电路，多个旁路电路，以及用于响应于位置替换高速缓冲存储器内的高速缓存行的电路 的令牌。 顺便提及，该令牌用于指示用于高速缓存行替换的候选高速缓存行。 令牌寄存器以环形配置连接，并且每个令牌寄存器与高速缓冲存储器的高速缓存行相关联，包括所有冗余高速缓存行。 通常，这些令牌寄存器之一包含令牌。 每个令牌寄存器具有分配指示电路。 分配指示电路用于指示与分配指示电路相关联的高速缓存行是否正在进行分配过程。 每个令牌寄存器还具有旁路电路。 响应于来自相关联的分配指示电路的指示，利用旁路电路将令牌从一个令牌寄存器传送到相邻令牌电路。

公开(公告)号：US5699288A

公开(公告)日：1997-12-16

申请号：US683292

申请日：1996-07-18

申请人： Song Chin Kim ,  Peichun Peter Liu ,  Rajinder Paul Singh

发明人： Song Chin Kim ,  Peichun Peter Liu ,  Rajinder Paul Singh

IPC分类号： G11C15/04

CPC分类号： G11C15/04

摘要： A compare circuit for a content-addressable memory within a computer system is disclosed. In accordance with a preferred embodiment of the present invention, a compare circuit for a content-addressable memory comprises a pair of storage node lines, a pair of compare lines, and two sets of transistors. The pair of storage node lines are complementary to each other and are connected to a memory cell of the content-addressable memory for determining a state of the memory cell. In a like manner, the pair of compare lines are also complementary to each other. The first set of transistors are four transistors connected in series to be enabled by a logical one from one of the storage node lines for allowing a signal from one of the compare lines to propagate to an output. The second set of transistors are also four transistors connected in series to be enabled by a logical zero from the same storage node line for allowing a signal from the other compare line to propagate to the output. Under the present invention, a signal from either compare line needs to propagate through only one level of transistors in order to reach the output.

摘要翻译： 公开了一种用于计算机系统内的可内容寻址存储器的比较电路。 根据本发明的优选实施例，用于内容寻址存储器的比较电路包括一对存储节点线，一对比较线和两组晶体管。 一对存储节点线彼此互补并且连接到内容寻址存储器的存储器单元，用于确定存储器单元的状态。 以同样的方式，一对比较线也是相互补充的。 第一组晶体管是串联连接的四个晶体管，以由来自存储节点线之一的逻辑一个使能，以允许来自一个比较线的信号传播到输出。 第二组晶体管也是串联连接的四个晶体管，以由来自相同存储节点线的逻辑零启用，以允许来自另一个比较线的信号传播到输出。 在本发明中，来自比较线的信号需要仅通过一个级别的晶体管传播才能达到输出。

公开(公告)号：US20110246695A1

公开(公告)日：2011-10-06

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： G06F12/00

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US07287103B2

公开(公告)日：2007-10-23

申请号：US11130911

申请日：2005-05-17

申请人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

发明人： Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Charles Ray Johns ,  Peichun Peter Liu

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G11C7/1006

摘要： A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR™ DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

摘要翻译： 提供了一种方法，装置和计算机程序产品，用于处理XDR（TM）DRAM存储器系统中的写掩码操作。 本发明消除了对双端口阵列的需要，因为在接收到数据时完成了掩码生成。 掩码计算需要较少的逻辑，因为256个可能的字节值中只有144个被解码。 掩码值生成并存储在掩码数组中。 独立地，写入数据被存储在写入缓冲器中。 掩码值用于生成写掩码命令。 一旦写掩码命令被发出，写入数据和掩码值被发送到多路复用器。 多路器使用掩码值对写入数据进行掩码，以便将掩蔽的数据存储在XDR DRAMS中。