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    Current limiting circuit for high-speed low-side driver outputs
    2.
    发明申请
    Current limiting circuit for high-speed low-side driver outputs 有权
    用于高速低端驱动器输出的限流电路

    公开(公告)号：US20050140425A1

    公开(公告)日：2005-06-30

    申请号：US10951969

    申请日：2004-09-28

    Applicant: Reed Adams ,  Thomas Schmidt ,  Suribhotla Rajasekhar

    Inventor： Reed Adams ,  Thomas Schmidt ,  Suribhotla Rajasekhar

    IPC: H03K5/153

    CPC classification number: H03K17/165 ,  H03K5/1252 ,  H03K17/0822

    Abstract: A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

    Abstract translation: 用于ABS制动系统的电磁线圈的FET开关晶体管可以在不超过基本上250ns内接通或断开。 当需要限制流过电流的电流时，不管是在电磁线圈的浪涌电流还是由于系统故障而导致FET开关晶体管快速导通的较高电流偏置电路被断开。 FET开关晶体管的高速开关导致通过晶体管的电流振铃，这导致电流检测器电路退出电流控制模式。 去电阻电路防止电流检测器离开电流控制模式，使得可以使用定时器来在FET开关晶体管在电流限制操作期间产生的热量损坏之前关闭FET开关晶体管。

    Internal protection circuit and method for on chip programmable poly fuses
    3.
    发明授权
    Internal protection circuit and method for on chip programmable poly fuses 有权
    片内可编程保险丝内部保护电路及方法

    公开(公告)号：US06469884B1

    公开(公告)日：2002-10-22

    申请号：US09472710

    申请日：1999-12-24

    Applicant: John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

    Inventor： John H. Carpenter, Jr. ,  Joseph A. Devore ,  Reed Adams ,  Ross Teggatz

    IPC: H02H322

    CPC classification number: G11C17/18

    Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.

    Abstract translation: 具有至少一个可编程熔丝（F1）和ESD电路（MN3，MN1）的集成电路（10）防止当在主电压电位（Vmain）上存在电压瞬变时熔丝（F1）被无意地烧断。 ESD电路优选地包括MOSFET开关，其由于电压瞬变而被耦合以比主熔丝编程开关（MNmain）更快地接通，从而确保主开关在电压瞬变期间保持关断以防止熔丝的无意的吹动 F1。 该电路非常适用于可编程逻辑器件（PLD），允许低至6伏的读取电压，并允许高达40伏的编程电压。

    CLAMPING CIRCUIT FOR HIGH-SPEED LOW-SIDE DRIVER OUTPUTS
    6.
    发明申请
    CLAMPING CIRCUIT FOR HIGH-SPEED LOW-SIDE DRIVER OUTPUTS 有权
    用于高速低边驱动器输出的钳位电路

    公开(公告)号：US20050140420A1

    公开(公告)日：2005-06-30

    申请号：US10798150

    申请日：2004-03-10

    Applicant: Reed Adams

    Inventor： Reed Adams

    IPC: H03K5/08 ,  H03K17/082 ,  H03K17/16 ,  H03L5/00

    CPC classification number: H03K17/0822 ,  H03K17/165

    Abstract: A clamp for a FET switch utilizes a surge detector to turn off one of two bias circuits for the FET. The first biasing circuit provides the current necessary for high speed switching. The second biasing circuit provides a lower biasing current. A resistor or other device is used to allow the measurement of BVdss on the integrated circuit where the surge detector is connected from a terminal of the conductive path of the FET to the gate thereof. The switching circuit allows the surge detector to turn on the FET to act as a self-clamp when there is a spike in the voltage applied to the FET, such as when turning off an inductive load.

    Abstract translation: 用于FET开关的钳位器使用浪涌检测器来关断FET的两个偏置电路中的一个。 第一偏置电路提供高速切换所需的电流。 第二偏置电路提供较低的偏置电流。 电阻器或其他器件用于允许在集成电路中测量BVdss，其中浪涌检测器从FET的导电路径的端子到其栅极连接。 当施加到FET的电压中存在尖峰时，例如当关闭感性负载时，开关电路允许浪涌检测器接通FET以用作自钳位。

    Power up clear (PUC) signal generators having input references that track process and temperature variations
    7.
    发明申请
    Power up clear (PUC) signal generators having input references that track process and temperature variations 审中-公开
    上电清零（PUC）信号发生器具有跟踪过程和温度变化的输入参考

    公开(公告)号：US20050212572A1

    公开(公告)日：2005-09-29

    申请号：US10811587

    申请日：2004-03-29

    Applicant: Reed Adams ,  Zbigniew Lata

    Inventor： Reed Adams ,  Zbigniew Lata

    IPC: H03K17/22 ,  H03L7/00

    CPC classification number: H03K17/223

    Abstract: A power up clear (PUC) signal is generated, based on a value of a supply voltage VCC. A first circuit element (such as an n-channel MOSFET MN0) of a first conductivity type having a first characteristic threshold voltage, and a second circuit element (such as p-channel MOSFET MP0) of a second conductivity type having a second characteristic threshold voltage, are provided in a PUC signal generating circuit. A first circuit portion (including MN0, R0) is configured to provide a first comparison input signal VIN−, and a second circuit portion (including MP0, R1, R2, and, switchably, R3) is configured to provide a second comparison input signal VIN+. A comparator COMP compares the first and second comparison input signals VIN−, VIN+, to cause the PUC signal to transition to an active state when one of the first and second comparison signals crosses another of the first and second comparison signals, in response to an increasing magnitude of the supply voltage during power up. The PUC signal generator automatically tracks (compensates for) device process variations and temperature changes, without reference to any externally supplied reference voltages or currents or bias voltages or currents.

    Abstract translation: 基于电源电压VCC的值产生上电清零（PUC）信号。 具有第一特征阈值电压的第一导电类型的第一电路元件（例如n沟道MOSFET MN 0）和具有第二导电类型的第二导电类型的第二电路元件（例如p沟道MOSFET MP 0） 特征阈值电压设置在PUC信号发生电路中。 第一电路部分（包括MN 0，R 0）被配置为提供第一比较输入信号VIN-，并且第二电路部分（包括MP 0，R 1，R 2和可切换地，R 3）被配置为 提供第二个比较输入信号VIN +。 比较器COMP响应于第一和第二比较输入信号VIN-，VIN +，使第一和第二比较信号中的一个与第一和第二比较信号中的另一个相交，从而使PUC信号转变到活动状态 上电期间电源电压的大小增加。 PUC信号发生器自动跟踪（补偿）器件工艺变化和温度变化，而不参考任何外部提供的参考电压或电流或偏置电压或电流。

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