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公开(公告)号：US5466484A
公开(公告)日：1995-11-14
申请号：US128282
申请日：1993-09-29
CPC分类号： G01K7/22 , H01L27/0802
摘要： A resistor structure (10) having a heating element (35) and a resistor (32), and a method of trimming the resistor (32). The heating element (35) is separated from the resistor (32) by a layer of dielectric material (19). The resistor (32) has a layer of resistive material (23) on an etch control layer (22). The resistor (32) is trimmed by providing current pulses (62) through the heating element (35). Heat generated by the current pulses flows to the resistor (32) and anneals or trims the resistor (32). A resistor trimming variable, e.g. a voltage across resistor contacts (30, 31), is monitored and the current pulses are modulated in accordance with the value of the resistor trimming variable (63). The trimming step is terminated when the desired resistance value of the resistor (32) is attained.
摘要翻译： 具有加热元件（35）和电阻器（32）的电阻器结构（10）以及修整电阻器（32）的方法。 加热元件（35）通过电介质材料（19）与电阻器（32）分离。 电阻器（32）在蚀刻控制层（22）上具有电阻材料层（23）。 通过提供通过加热元件（35）的电流脉冲（62）来修整电阻器（32）。 由电流脉冲产生的热量流向电阻器（32）并退火或修整电阻器（32）。 电阻修整变量，例如 监视电阻触头（30,31）两端的电压，并根据电阻微调变量（63）的值调制电流脉冲。 当达到电阻器（32）的期望电阻值时，修整步骤终止。
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2.发明授权
公开(公告)号：US4995953A
公开(公告)日：1991-02-26
申请号：US428580
申请日：1989-10-30
申请人： Renwin J. Yee
发明人： Renwin J. Yee
IPC分类号： G01L9/00 , H01L21/3063
CPC分类号： G01L9/0042 , H01L21/3063
摘要： A semiconductor membrane is fabricated in a substrate by applying a voltage to a Schottky diode or a capacitor formed on a surface of the substrate to create a depletion region in the substrate. The substrate is exposed to an electrochemical, anisotropic etch solution. Etching terminates at the depletion region, thus forming a membrane having a thickness defined by the thickness of the depletion region.
摘要翻译： 通过向形成在衬底表面上的肖特基二极管或电容器施加电压，在衬底中制造半导体膜，以在衬底中形成耗尽区。 将基板暴露于电化学，各向异性蚀刻溶液中。 蚀刻在耗尽区终止，从而形成具有由耗尽区的厚度限定的厚度的膜。
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公开(公告)号：US5610495A
公开(公告)日：1997-03-11
申请号：US262305
申请日：1994-06-20
CPC分类号： H02J7/0019 , H01M10/48 , Y10S320/13
摘要： A battery monitoring circuit (10) sequentially samples individual voltages across a string of serially coupled battery cells (12-18). A control circuit (32) controls first and second multiplexers (34,42) to sample each battery voltage for an over-voltage condition. A comparator (52) detects an over-voltage condition by comparing a divided down battery voltage against a reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (26) in the battery cell conduction path. The battery cells are further sequentially sampled for an under-voltage fault. The comparator detects an under-voltage condition by comparing a second divided down battery voltage against the reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (24) in the battery cell conduction path.
摘要翻译： 电池监视电路（10）顺序地对串联的串联电池单元（12-18）的各个电压进行采样。 控制电路（32）控制第一和第二多路复用器（34,42）以对每个电池电压进行采样以用于过电压状态。 比较器（52）通过将分压的电池电压与参考值进行比较来检测过电压状态。 在通过电池单元传导路径中的晶体管（26）检测到故障状态时，通过电池单元的传导路径被禁用。 对于欠压故障，电池单元进一步顺序采样。 比较器通过比较第二分压电池电压与参考值来检测欠电压状况。 在通过电池单元传导路径中的晶体管（24）检测到故障状态时，通过电池单元的传导路径被禁止。
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公开(公告)号：US5376875A
公开(公告)日：1994-12-27
申请号：US160764
申请日：1993-12-03
CPC分类号： H02J7/008
摘要： A battery charger status monitor circuit (40) for monitoring the status of a battery (12) charged with current pulses. The current pulses charging the battery (12) are reduced in frequency and duty cycle as the battery approaches a fully charged condition. By monitoring the number of current pulses charging the battery within a predetermined time period, the charge status of the battery (12) is determined. If no pulses are detected within the predetermined time period, the battery (12) is fully charged. A counter (47) is incremented by a clock signal. A charge signal resets the counter (47). The charge signal corresponds to the current pulses charging the battery. If the counter (47) reaches a predetermined count, the clock and charge signals are disabled. Reaching the predetermined count before resetting indicates the battery (12) is fully charged. When the counter is below the predetermined count, the battery (12) is being charged.
摘要翻译： 一种用于监视充电电流脉冲的电池（12）的状态的电池充电器状态监视电路（40）。 当电池接近完全充电状态时，对电池（12）充电的电流脉冲的频率和占空比会降低。 通过监视在预定时间段内对电池充电的电流脉冲数，确定电池（12）的充电状态。 如果在预定时间段内没有检测到脉冲，则电池（12）被充满电。 计数器（47）由时钟信号递增。 计费信号复位计数器（47）。 充电信号对应于对电池充电的电流脉冲。 如果计数器（47）达到预定计数，则时钟和充电信号被禁用。 在复位前达到预定的计数表示电池（12）已充满电。 当计数器低于预定计数时，电池（12）正在充电。
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公开(公告)号：US5422559A
公开(公告)日：1995-06-06
申请号：US161627
申请日：1993-12-06
CPC分类号： H02J7/008
摘要： A pulsed battery charger circuit (11) for charging a battery (28). A control circuit (17) is responsive to a sense circuit (16) that monitors the battery voltage. The control circuit (17) pulses a first current source (25) or a second current source (20). An amplifier (14) is responsive to the first (25) and second (20) current sources for generating first and second predetermined voltages between a drive output (12) and a sense input (13). The first current source (25) is pulsed when the sense circuit (16) senses the battery voltage to be less than a first threshold voltage. The second current source (20) is pulsed when the sense circuit (16) senses the battery voltage to be greater than the first threshold voltage. Both the first (25) and second (20) current sources are disabled when the sense circuit (16) senses the battery voltage to be greater than a second threshold voltage.
摘要翻译： 一种用于对电池（28）充电的脉冲电池充电器电路（11）。 控制电路（17）响应监视电池电压的检测电路（16）。 控制电路（17）对第一电流源（25）或第二电流源（20）进行脉冲。 放大器（14）响应于第一（25）和第二（20）电流源，用于在驱动输出（12）和感测输入（13）之间产生第一和第二预定电压。 当感测电路（16）感测到电池电压小于第一阈值电压时，第一电流源（25）是脉冲的。 当感测电路（16）感测到电池电压大于第一阈值电压时，第二电流源（20）被脉冲。 当感测电路（16）感测到电池电压大于第二阈值电压时，第一（25）和第二（20）电流源都被禁用。
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公开(公告)号：US5327100A
公开(公告)日：1994-07-05
申请号：US24142
申请日：1993-03-01
CPC分类号： H03F3/3071 , H03F3/45094 , H03F2203/45022 , H03F2203/45028 , H03F2203/45178 , H03F2203/45188 , H03F2203/45258 , H03F2203/45374 , H03F2203/45496 , H03F2203/45674 , H03F2203/45696
摘要： An operational amplifier enhances its negative slew rate by providing more base current to a bottom PNP output drive transistor. A large signal applied at the inverting input of the operational amplifier unbalances the differential input stage and provides maximum current through a current mirror circuit to the base of the PNP output transistor. A transistor is biased on by sufficient current flow through the current mirror circuit to draw even more base current from the base of the PNP output transistor and thereby enhance its negative slew rate.
摘要翻译： 运算放大器通过向底部PNP输出驱动晶体管提供更多的基极电流来增强其负压摆率。 施加在运算放大器的反相输入端的大信号不平衡差分输入级，并通过电流镜电路提供最大电流至PNP输出晶体管的基极。 晶体管被充分的电流流过电流镜电路而被偏置，以从PNP输出晶体管的基极吸取更多的基极电流，从而增强其负的压摆率。
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公开(公告)号：US5818201A
公开(公告)日：1998-10-06
申请号：US814684
申请日：1997-03-11
CPC分类号： H02J7/008 , H02J7/0016 , H02J7/0026 , H02J7/0036
摘要： A battery charge control circuit (10) senses the charge condition of cells in a battery pack (12, 14, 16, 18) using a measurement circuit (51). Upon detection of a single under-voltage cell, the charge control circuit is placed in a sleep mode. Pack sense circuit (240) senses when the battery pack is placed in a charger. If circuit (10) was in a sleep mode, it is awakened. If any cell is measured over-voltage, the status is checked versus the other cells. If all the cells are over-voltage, the battery is considered balanced. If one or more cells are not over-voltage, a control circuit (32) activates a discharge transistor (212, 214, 216, 218), discharging the cell within a hysteresis voltage below the over-voltage limit. Charge balancing of cells is continued until the cells are within a programmable hysteresis voltage of each other.
摘要翻译： 电池充电控制电路（10）使用测量电路（51）感测电池组（12,14,16,18）中的电池的充电状态。 在检测到单个欠压单元时，充电控制电路处于睡眠模式。 包感测电路（240）感测电池组何时被放置在充电器中。 如果电路（10）处于睡眠模式，则唤醒。 如果任何电池被测量过电压，则检查状态与其他电池。 如果所有电池都是过电压，则认为电池是平衡的。 如果一个或多个电池不是过电压，则控制电路（32）激活放电晶体管（212,214,216,218），使电池在低于过电压限制的滞后电压内放电。 电池的电荷平衡继续进行，直到电池在可编程的滞后电压之内。
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公开(公告)号：US5635893A
公开(公告)日：1997-06-03
申请号：US552278
申请日：1995-11-02
CPC分类号： G01K7/22 , H01L27/0802
摘要： A resistor structure (10) having a heating element (35) and a resistor (32), and a method of trimming the resistor (32). The heating element (35) is separated from the resistor (32) by a layer of dielectric material (19). The resistor (32) has a layer of resistive material (23) on an etch control layer (22). The resistor (32) is trimmed by providing current pulses (62) through the heating element (35). Heat generated by the current pulses flows to the resistor (32) and anneals or trims the resistor (32). A resistor trimming variable, e.g. a voltage across resistor contacts (30, 31), is monitored and the current pulses are modulated in accordance with the value of the resistor trimming variable (63). The trimming step is terminated when the desired resistance value of the resistor (32) is attained.
摘要翻译： 具有加热元件（35）和电阻器（32）的电阻器结构（10）以及修整电阻器（32）的方法。 加热元件（35）通过电介质材料（19）与电阻器（32）分离。 电阻器（32）在蚀刻控制层（22）上具有电阻材料层（23）。 通过提供通过加热元件（35）的电流脉冲（62）来修整电阻器（32）。 由电流脉冲产生的热量流向电阻器（32）并退火或修整电阻器（32）。 电阻修整变量，例如 监视电阻触头（30,31）两端的电压，并根据电阻微调变量（63）的值调制电流脉冲。 当达到电阻器（32）的期望电阻值时，修整步骤终止。
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公开(公告)号：US5204639A
公开(公告)日：1993-04-20
申请号：US873855
申请日：1992-04-27
申请人： Bradley T. Moore , Robert L. Vyne , Renwin J. Yee
发明人： Bradley T. Moore , Robert L. Vyne , Renwin J. Yee
IPC分类号： H03F1/08
CPC分类号： H03F1/083
摘要： A monolithic operational amplifier (10) having an Miller loop compensation network (13) with improved capacitive drive. The monolithic operational amplifier (10) has an input stage (11), an output stage (12), and a compensation network (13). The compensation network (13) provides negative feedback between an output node (19) of the output stage (12) and an input node (16) of the output stage (12). The compensation network (13) has a compensation capacitor (26), a resistor (27), an isolation resistor (33), a shunt capacitor (28), and an isolation transistor (25). The compensation network (13) creates a dominant pole, a zero and a nondominant pole having a higher frequency than the zero. The nondominant pole improves a gain margin while preserving sufficient phase margin. The isolation transistor (25) provides improved capacitive drive.
摘要翻译： 具有具有改进的电容驱动的米勒环路补偿网络（13）的单片运算放大器（10）。 单片运算放大器（10）具有输入级（11），输出级（12）和补偿网络（13）。 补偿网络（13）在输出级（12）的输出节点（19）和输出级（12）的输入节点（16）之间提供负反馈。 补偿网络（13）具有补偿电容器（26），电阻器（27），隔离电阻器（33），并联电容器（28）和隔离晶体管（25）。 补偿网络（13）产生具有比零更高频率的主极，零极和非主导极。 非优势极提高增益裕度，同时保持足够的相位裕量。 隔离晶体管（25）提供改进的电容驱动。
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公开(公告)号：US5074152A
公开(公告)日：1991-12-24
申请号：US633828
申请日：1990-12-24
IPC分类号： G01L9/00
CPC分类号： G01L9/0054
摘要： Leakage current is reduced in a piezoresistive transducer by forming a leakage barrier around a piezoresistive element of a piezoresistive transducer. The leakage barrier prevents the formation of a parasitic leakage path in the substrate thereby reducing the leakage current flowing through sections of the piezoresistive element, and stabilizing the resistance value and the output voltage of the piezoresistive transducer.
摘要翻译： 在压阻式换能器中通过在压阻换能器的压阻元件周围形成泄漏屏障来减小泄漏电流。 泄漏屏障防止在衬底中形成寄生泄漏路径，从而减少流过压阻元件的部分的漏电流，并稳定压阻式换能器的电阻值和输出电压。
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