公开(公告)号：US07642938B2

公开(公告)日：2010-01-05

申请号：US12028469

申请日：2008-02-08

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03M7/04

CPC classification number: H03M7/16 ,  H03M7/165

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract translation: 本发明涉及格雷码及其转换为符号和幅度表示。 格雷码用于闪存ADC（模数转换器），将模拟波形转换为采样二进制值。 这可以通过温度计代码来实现，并且本发明解决了由于不确定的温度计代码值导致的误差传播的问题。 特别地，本发明提供了一种格雷码，用于符号和幅度转换器，其被布置为产生除了符号位之外的其输出的比特，对于格雷码的相同代码，其与来自符号位改变值的边界相同的距离 格雷码按照它们的价值排列。

公开(公告)号：US5606347A

公开(公告)日：1997-02-25

申请号：US474640

申请日：1995-06-07

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G06F12/02 ,  G09G5/02 ,  G09G5/39 ,  G09G5/04

CPC classification number: G09G5/39 ,  G06F12/0207 ,  G09G5/022 ,  G09G2352/00

Abstract: A memory device 72 is provided which includes a plurality of data storage locations each having an associated address and arranged as a plurality of planes 76. A data port 78, 86 is coupled to each of the planes 76. Control circuitry 78, 80, 82 is provided and includes inputs receiving an address and a mode control signal, the control circuitry operable in the first mode to provide access through data port 78, 86 to an addressed location in each of the plurality of planes 76 and in a second mode to provide access through the data port 78, 86 to a plurality of storage locations in a selected one of the planes 76.

Abstract translation: 提供存储器件72，其包括多个数据存储位置，每个存储位置具有相关联的地址并被布置为多个平面76.数据端口78,86耦合到每个平面76.控制电路78,80,82 并且包括接收地址和模式控制信号的输入，所述控制电路可在第一模式中操作以提供通过数据端口78,86到达多个平面76中的每一个中的寻址位置的访问，并且以第二模式提供 通过数据端口78,88访问所选择的一个平面76中的多个存储位置。

公开(公告)号：US5546553A

公开(公告)日：1996-08-13

申请号：US359324

申请日：1994-12-15

Applicant: Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

Inventor： Iain C. Robertson ,  Jeffrey L. Nye ,  Michael D. Asal ,  Graham B. Short ,  Richard D. Simpson ,  James G. Littleton

IPC: G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/06 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395 ,  G06F12/00

CPC classification number: G06F3/1438 ,  G06F3/14 ,  G09G5/06 ,  G09G5/363 ,  G09G5/39 ,  G09G5/395 ,  G09G2360/126 ,  G09G5/001

Abstract: A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

公开(公告)号：US4494187A

公开(公告)日：1985-01-15

申请号：US350960

申请日：1982-02-22

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G06F9/32 ,  G06F12/06 ,  G11C17/12 ,  G06F13/00

CPC classification number: G06F12/0607 ,  G06F9/32 ,  G11C17/12

Abstract: A system for real-time digital processing employs a single-chip microcomputer device having a high-speed on-chip program ROM and a separate data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program ROM has a low-level precharge circuit with feedback to improve speed or access time.

Abstract translation: 一种用于实时数字处理的系统采用具有高速片上程序ROM和独立数据RAM的单片微机器件，具有用于程序和数据的单独的地址和数据路径。 外部程序地址总线允许在扩展模式下进行片外程序提取，外部数据总线返回操作码。 总线交换模块允许在特殊情况下在单独的内部程序和数据总线之间进行转移。 内部总线为16位，ALU和累加器为32位。 乘法器电路产生与ALU分离的单状态16x16乘法功能，具有32位输出到ALU。 ALU的一个输入通过带符号扩展的0到15位移位器。 片上程序ROM具有具有反馈的低电平预充电电路，以提高速度或访问时间。

公开(公告)号：US07191199B2

公开(公告)日：2007-03-13

申请号：US10640453

申请日：2003-08-13

Applicant: Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

Inventor： Richard D. Simpson ,  Graeme Swanson ,  Konstantinos Venos

IPC: G06F15/00

CPC classification number: G06F7/544 ,  G06F2207/5442

Abstract: Computing an absolute difference includes receiving a first value and a second value. Propagate terms are determined according to the first value and the second value at one or more adders (24). The second value is subtracted from the first value using the propagate terms to yield a subtraction difference. It is determined at one or more correctors (26) whether the subtraction difference is negative. If the subtraction difference is negative, the subtraction difference is modified according to the propagate terms to compute an absolute difference between the first value and the second value. Otherwise, the subtraction difference is reported as the absolute difference between the first value and the second value.

Abstract translation: 计算绝对差异包括接收第一值和第二值。 根据在一个或多个加法器（24）处的第一值和第二值确定传播项。 使用传播项从第一个值中减去第二个值，以产生减法差。 在一个或多个校正器（26）中确定减法差是否为负。 如果减法差为负，则根据传播项修改减法差，以计算第一值和第二值之间的绝对差。 否则，减法差被报告为第一值和第二值之间的绝对差。

公开(公告)号：US06986089B2

公开(公告)日：2006-01-10

申请号：US10256723

申请日：2002-09-27

Applicant: Anthony M. Hill ,  Richard D. Simpson

Inventor： Anthony M. Hill ,  Richard D. Simpson

IPC: G01R31/28 ,  G06F13/38

CPC classification number: G01R31/318575 ,  G01R31/31721

Abstract: In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Abstract translation: 在具有同步预置或清除能力的可扫描D主从触发器电路中，从锁存器的输出通过扫描使能信号选通，形成扫描数据输出信号。 该输出门控的扫描输出数据允许相当简化的输入逻辑。 这种简化还提供了输入逻辑中的晶体管的尺寸和数量的减少。 这在复杂的处理器芯片中又相当于数万次，导致芯片功率和硅面积使用量大幅降低。

公开(公告)号：US5079742A

公开(公告)日：1992-01-07

申请号：US386849

申请日：1989-07-28

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: G11C17/12

CPC classification number: G11C17/12

Abstract: A read-only memory suitable for use as the control ROM of a microprocessor has each output line divided into first and second parts. Memory elements connected to the first parts are responsive to early-occurring input signals and memory elements connected to the second parts are responsive to late-occurring input signals. Switch means are provided to enable the output signals from the second parts of the output lines to be generated in response to a late-occurring input signal independently of the loading of the memory elements connected to the first parts of the output lines.

Abstract translation: 适合用作微处理器的控制ROM的只读存储器将每条输出线分成第一和第二部分。 连接到第一部分的存储元件响应于早期输入信号，并且连接到第二部分的存储元件响应于晚期输入信号。 提供开关装置，以使得来自输出线的第二部分的输出信号能够响应于晚期发生的输入信号而产生，而与连接到输出线的第一部分的存储元件的负载无关。

公开(公告)号：US5005193A

公开(公告)日：1991-04-02

申请号：US374194

申请日：1989-06-29

Applicant: Richard D. Simpson

Inventor： Richard D. Simpson

IPC: H03K5/15

CPC classification number: H03K5/15093

Abstract: A clock generating circuit for use in a signal processing circuit to enable it to be synchronized with other circuits in response to a reset signal uses a multi-state circuit which is cyclically stepped through its states by a clock drive signal and a decoder responsive to the state of the multi-state circuit to produce the required clock pulses. The reset signal is used to stop the multi-state circuit at a particular state and hold it there for a period of time enabling other similar clock pulse generating circuits to reach the same state and be held there. At the end of the period of time the multi-state circuits resume their cyclic stepping with all the circuits in synchronism.

Abstract translation: 用于在信号处理电路中使其能够响应于复位信号与其它电路同步的时钟发生电路使用多状态电路，该多状态电路通过时钟驱动信号和解码器对其状态进行循环地步进， 状态电路以产生所需的时钟脉冲。 复位信号用于在特定状态下停止多状态电路并将其保持在一段时间，使得其他类似的时钟脉冲发生电路能够达到相同的状态并保持在那里。 在这段时间结束时，多状态电路与所有电路同步地恢复循环步进。

公开(公告)号：US4858167A

公开(公告)日：1989-08-15

申请号：US285359

申请日：1988-12-14

Applicant: Richard D. Simpson ,  Derek Roskell

Inventor： Richard D. Simpson ,  Derek Roskell

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/508

CPC classification number: G06F7/506

Abstract: A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.

Abstract translation: 使用动态晶体管逻辑来描述二进制加法器电路，其中对于高速进位传播，加法器级被成对或成对地分组，并且在每个组中提供附加的动态逻辑装置以控制在进位传播路径中串联连接的单个晶体管 在集团上。 在具体实施例中使用的晶体管是MOS晶体管，但是其中的一些或全部可以被结FET或双极晶体管代替。

公开(公告)号：US4849920A

公开(公告)日：1989-07-18

申请号：US839004

申请日：1986-03-12

Applicant: Richard D. Simpson ,  Michael D. Asal

Inventor： Richard D. Simpson ,  Michael D. Asal

IPC: G06F7/00 ,  G06F7/74 ,  G06F7/76 ,  H03M7/00

CPC classification number: G06F7/74

Abstract: The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group. The units are coupled together so that a representation from a preceding unit blocks the output of a representation from a subsequent unit.

Abstract translation: 通过将反相位并行地并入到各个或非门（61至68）的输入端来检测输入号码中的“1”位的位置，其另一个输入端连接到动态域链的节点 效应晶体管（A1至A8），沿着该晶体管传播“O”。 两个O在NOR门的输入端的重合使得它产生一个“1”输出，表示输入号码的结尾“1”的位置。 NOR门（L1〜L8）的输出端连接到场效应晶体管阵列（LA）的列导体，该场效应晶体管阵列（LA）在行导体阵列上平行生成，反相，二进制编码形成对应于NOR 门产生“1”输出。 该装置可以响应于输入号码的相邻组的每一组而分成若干单元（U1至U4），每个单元产生其组中的端“1”的位置的表示。 这些单元耦合在一起，使得来自前一单元的表示阻止来自后续单元的表示的输出。