公开(公告)号：US06362835B1

公开(公告)日：2002-03-26

申请号：US08156541

申请日：1993-11-23

Applicant: Paul M. Urbanus ,  Robert J. Gove

Inventor： Paul M. Urbanus ,  Robert J. Gove

IPC: G09G300

CPC classification number: G09G3/34 ,  G09G3/20 ,  G09G3/2022 ,  G09G3/346 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2320/066 ,  G09G2320/0666

Abstract: A method and system for adjusting the brightness and contrast of a digital pulse-width modulated display without scaling the input image data. Brightness is adjusted by changing the duty cycle of a displayed pixel either by altering the bit display durations, or by turning the pixel on during blanking periods 36. The contrast ratio may be altered by changing the display duration of at least one of the MSBs differently than the display duration of at least one of the LSBs. Contrast may be increased by extending the MSB display periods 50 and shortening the LSB display periods 52. Contrast may be decreased by shortening the MSB display periods 56 and extending the LSB display periods 58. The color tint of the displayed image may be altered by individually changing the brightness of the constituent colors.

Abstract translation: 一种用于调节数字脉冲宽度调制显示器的亮度和对比度而不缩放输入图像数据的方法和系统。 通过改变比特显示持续时间来改变所显示的像素的占空比，或者通过在消隐期​​间36期间转动像素来调节亮度。可以通过改变至少一个MSB的显示持续时间来改变对比度 比LSB中的至少一个的显示持续时间长。 可以通过延长MSB显示周期50并缩短LSB显示周期52来增加对比度。可以通过缩短MSB显示周期56并延长LSB显示周期58来减小对比度。可以通过单独地改变显示图像的色调 改变组成颜色的亮度。

公开(公告)号：US06232936B1

公开(公告)日：2001-05-15

申请号：US08415101

申请日：1995-03-31

Applicant: Robert J. Gove ,  Jeffrey B. Sampsell

Inventor： Robert J. Gove ,  Jeffrey B. Sampsell

IPC: G09G334

CPC classification number: G02B26/0841

Abstract: A method and device for increasing the effective horizontal resolution of a display device. One embodiment forms a cardinal array of digital micromirror elements by staggering alternate rows in an array. According to a second embodiment, an ordinal pixel array 57, is converted to a cardinal pixel array, by grouping SLM elements 59, 61, 63, and 65 into a pixel block 58. All of the elements in a pixel block are controlled in unison such that the pixel block acts like a single pixel. Rows of pixel blocks 67 and 69 are offset to provide the effect of a cardinal array of pixels without the decrease in efficiency sometimes associated with cardinal pixel arrays.

Abstract translation: 一种用于增加显示装置的有效水平分辨率的方法和装置。 一个实施例通过交错阵列中的交替行来形成数字微镜元件的基数阵列。 根据第二实施例，通过将SLM元件59,61,63和65分组成像素块58，将序数像素阵列57转换为基本像素阵列。像素块中的所有元素被一致地控制 使得像素块像单个像素那样起作用。 像素块67和69的行被偏移以提供像素阵列的效果，而不会有效地与主要像素阵列相关联的效率的降低。

公开(公告)号：US5973733A

公开(公告)日：1999-10-26

申请号：US707045

申请日：1996-08-30

Applicant: Robert J. Gove

Inventor： Robert J. Gove

IPC: H04N5/14 ,  H04N5/232 ,  H04N5/77 ,  H04N5/228

CPC classification number: H04N5/23264 ,  H04N5/145 ,  H04N5/23248 ,  H04N5/23254 ,  H04N5/77

Abstract: A system (26) for stabilizing a video recording of a scene (20, 22, & 24) made with a video camera (34) is provided. The video recording may include video data (36) and audio (38) data. The system (26) may include source frame storage (64) for storing source video data (36) as a plurality of sequential frames. The system (26) may also include a processor (50) for detecting camera movement occurring during recording and for modifying the video data (36) to compensate for the camera movement. Additionally the system (26) may include destination frame storage (70) for storing the modified video data as plurality of sequential frames.

Abstract translation: 提供一种用于稳定由摄像机（34）制成的场景（20,22，＆24）的视频记录的系统（26）。 视频记录可以包括视频数据（36）和音频（38）数据。 系统（26）可以包括用于将源视频数据（36）存储为多个顺序帧的源帧存储（64）。 系统（26）还可以包括处理器（50），用于检测在记录期间发生的相机移动，并且用于修改视频数据（36）以补偿相机运动。 另外，系统（26）可以包括用于将修改的视频数据存储为多个连续帧的目的地帧存储（70）。

公开(公告)号：US5748250A

公开(公告)日：1998-05-05

申请号：US533409

申请日：1995-09-25

Applicant: Vishal Markandey ,  Robert J. Gove

Inventor： Vishal Markandey ,  Robert J. Gove

IPC: H04N7/01 ,  H04N5/14 ,  H04N5/44 ,  H04N5/74

CPC classification number: H04N7/012 ,  H04N5/145 ,  H04N5/7458 ,  H04N2005/7466

Abstract: A line generator (31) for receiving fields of pixel data sampled from a video input signal and for generating additional lines of pixel data so that the display frames will have more lines than the fields. The line generator (31) has a motion detector (31a) that determines, on a pixel by pixel basis, whether some part of the current field is in motion. A motion signal from the motion detector (31a) is used to select between outputs of two or more pixel generators (31b, 31c). One of the pixel generators (31b) provides pixel values that are better suited for display when the image is not in motion. The other pixel generator (31c) provides pixel values that are better suited for display when the image is in motion.

Abstract translation: 一种线生成器（31），用于接收从视频输入信号采样的像素数据的场，并产生附加的像素数据行，使得显示帧将具有比场多的行。 线发生器（31）具有运动检测器（31a），该运动检测器（31a）逐像素地确定当前场的某些部分是否运动。 来自运动检测器（31a）的运动信号用于在两个或更多个像素发生器（31b，31c）的输出之间进行选择。 像素发生器（31b）之一提供当图像不运动时更适合于显示的像素值。 另一像素生成器（31c）提供当图像运动时更适合于显示的像素值。

公开(公告)号：US5729245A

公开(公告)日：1998-03-17

申请号：US403532

申请日：1995-03-14

Applicant: Robert J. Gove ,  Richard C. Meyer ,  Stephen W. Marshall ,  Gary L. Sextro

Inventor： Robert J. Gove ,  Richard C. Meyer ,  Stephen W. Marshall ,  Gary L. Sextro

IPC: G09G3/00 ,  G09G3/34 ,  G09G3/36 ,  G09G5/34 ,  H04N9/30

CPC classification number: G09G3/002 ,  G09G3/34 ,  G09G5/346 ,  H04N9/30 ,  G09G2320/0693 ,  G09G3/346 ,  G09G3/3611

Abstract: A method and structure for a display system having multiple spatial light modulators (SLMs) (16), each of which contributes an image of one color that is perceived by the viewer as a combined image. The SLMs (16) have more rows and columns of pixel elements (42) than rows or columns of pixel data to be displayed. A window of "active" pixel elements (42) can be shifted up and down or right and left by selecting which pixel elements (42) are to receive data. The addressing circuit (31, 31a, 35, 35a) of each SLM 16 can be controlled so as to accomplish this shifting.

Abstract translation: 一种具有多个空间光调制器（SLM）（16）的显示系统的方法和结构，每个空间光调制器（16）将观看者感知到的一种颜色的图像作为组合图像。 SLM（16）具有比要显示的像素数据的行或列更多的行和列像素元素（42）。 通过选择哪些像素元素（42）来接收数据，可以向上或向下或向左或向右移动“活动”像素元素（42）的窗口。 可以控制每个SLM 16的寻址电路（31,3a，35,35a），以实现这种移位。

公开(公告)号：US5671018A

公开(公告)日：1997-09-23

申请号：US384986

申请日：1995-02-07

Applicant: Kazuhiro Ohara ,  Vishal Markandey ,  Robert J. Gove

Inventor： Kazuhiro Ohara ,  Vishal Markandey ,  Robert J. Gove

IPC: H04N5/44 ,  H04N5/74 ,  H04N7/01 ,  H04N9/64

CPC classification number: H04N7/0137 ,  H04N7/012 ,  H04N9/64

Abstract: A motion adaptive method for vertically scaling an image. The image data is analyzed to obtain a motion magnitude value for each pixel (31). The pixel data is then processed with two scaling processes (35, 36), performed in parallel. One scaling process is better suited for low motion images and the other is better suited for high motion images. The motion magnitude value is used to select between or combine (38) the pixel data outputs of the two scaling processes (35, 36).

Abstract translation: 一种用于垂直缩放图像的运动自适应方法。 分析图像数据以获得每个像素的运动幅度值（31）。 然后用两个平行进行的缩放处理（35,36）处理像素数据。 一个缩放过程​​更适合于低运动图像，另一个更适合于高运动图像。 运动幅度值用于在两个缩放处理（35,36）之间选择或组合（38）像素数据输出。

公开(公告)号：US5651127A

公开(公告)日：1997-07-22

申请号：US209123

申请日：1994-03-08

Applicant: Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Christopher J. Read ,  Iain Robertson ,  Nicholas Ing Simmons

Inventor： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Christopher J. Read ,  Iain Robertson ,  Nicholas Ing Simmons

IPC: G06F9/345 ,  G06F9/38 ,  G06F13/28 ,  G09G5/393 ,  G06F91/26 ,  G06F9/34 ,  G06F12/00 ,  G06F12/14

CPC classification number: G09G5/393 ,  G06F13/28 ,  G06F9/345 ,  G06F9/3879

Abstract: This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may optionally form the predetermined combination of starting address and address value of guide table entry by adding the address value to the prior block starting address or by adding the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses. In the preferred embodiment, memory, a data processor and a data transfer controller performing the above memory accesses is constructed in a single semiconductor chip. The data transfer controller may access external memory in the same manner as on-chip memory.

Abstract translation: 本发明是对存储器存取地址的控制方式。 本发明的数据处理装置包括存储器，控制电路，引导表和地址产生电路。 控制电路接收分组传送请求和分组传送参数。 分组传送参数包括起始地址，指导表条目的数目和表指针。 指南表包括指南表条目，每个指南表条目具有定义地址块的地址值和维度值。 表指针最初指向指南表中的第一个指南表项。 地址生成电路形成与每个引导表条目相对应的用于存储器访问的地址块集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。 地址块由维度值形成。 在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。 地址产生电路可以通过将地址值添加到先前块开始地址或通过将引导表值添加到起始地址来可选地形成指南表入口的起始地址和地址值的预定组合。 存储器访问可以是从地址块读取的存储器或写入地址块的存储器。 在优选实施例中，执行上述存储器访问的存储器，数据处理器和数据传输控制器被构造在单个半导体芯片中。 数据传输控制器可以以与片上存储器相同的方式访问外部存储器。

公开(公告)号：US5528317A

公开(公告)日：1996-06-18

申请号：US188266

申请日：1994-01-27

Applicant: Robert J. Gove ,  Donald B. Doherty

Inventor： Robert J. Gove ,  Donald B. Doherty

IPC: H04N9/30 ,  H04N9/12

CPC classification number: H04N9/30

Abstract: A method and apparatus for synchronizing display timing in a digital television system with a pixel addressable display having a color wheel is disclosed. The display timing circuit 22 includes phase comparator 40, for comparing the phase of a wheel index signal generated by a color wheel 20 with the phase of a frame synchronization signal indicating that a complete frame is ready to be displayed. Display timing circuit 22 further comprises a color wheel synchronization generator 42 which generates a color wheel synchronization signal in response to a phase difference value produced by phase comparator 40. The color wheel synchronization signal is used to increase, decrease, or maintain the speed of color wheel 20 to achieve a known phase relationship between the frame synchronization signal and the wheel index signal. Display timing circuit 22 further comprises a clock generator applicable to generate a display master clock signal having a known frequency relation to the wheel index signal.

Abstract translation: 公开了一种用于将数字电视系统中的显示定时与具有色轮的像素可寻址显示器同步的方法和装置。 显示定时电路22包括相位比较器40，用于将由色轮20产生的车轮指标信号的相位与指示完整帧准备显示的帧同步信号的相位进行比较。 显示定时电路22还包括色轮同步发生器42，其根据由相位比较器40产生的相位差产生色轮同步信号。色轮同步信号用于增加，降低或维持颜色速度 以实现帧同步信号和车轮索引信号之间已知的相位关系。 显示定时电路22还包括时钟发生器，其适用于产生与车轮指标信号具有已知频率关系的显示主时钟信号。

公开(公告)号：US5497197A

公开(公告)日：1996-03-05

申请号：US147801

申请日：1993-11-04

Applicant: Robert J. Gove ,  Donald B. Doherty ,  Stephen W. Marshall ,  Carl W. Davis ,  Joseph G. Egan ,  Richard C. Meyer ,  Jeffrey B. Sampsell ,  Scott D. Heimbuch

Inventor： Robert J. Gove ,  Donald B. Doherty ,  Stephen W. Marshall ,  Carl W. Davis ,  Joseph G. Egan ,  Richard C. Meyer ,  Jeffrey B. Sampsell ,  Scott D. Heimbuch

IPC: H04N5/922 ,  H04N5/14 ,  H04N5/44 ,  H04N5/74 ,  H04N5/937 ,  H04N7/26 ,  H04N7/30 ,  H04N7/50 ,  H04N11/04 ,  H04N7/12 ,  H04N11/02

CPC classification number: H04N5/14 ,  H04N19/436 ,  H04N19/61 ,  H04N5/7458 ,  H04N9/3147 ,  H04N19/30 ,  H04N2005/7466 ,  H04N7/0122

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract translation: 提供了一种用于将数据打包到视频处理器中的系统（30）。 系统（30）包括解复用器（32），第一和第二先进先出缓冲存储器（34）和（36）以及多路复用器（38）。 解复用器（32）将视频数据的区域划分为第一和第二部分（42）和（44）。 第一和第二部分（42）和（44）分别存储在第一先进先出缓冲存储器（34）和（36）中。 多路复用器（38）将来自第一先进先出缓冲存储器（34）的一行与来自第二先进先出缓冲存储器（36）的一行组合以形成一行用于处理。

公开(公告)号：US5491510A

公开(公告)日：1996-02-13

申请号：US161831

申请日：1993-12-03

Applicant: Robert J. Gove

Inventor： Robert J. Gove

IPC: H04N7/18 ,  A61B19/00 ,  H04N5/232 ,  H04N5/64

CPC classification number: H04N5/64 ,  A61B90/36 ,  H04N5/23293

Abstract: A visual information system to capture an input image using a camera 22, manipulate the image using processor 28, and project the processed image using optics 33 to superimpose the processed image on the actual object being observed by a viewer. Processing is done in real-time to allow the viewer to see both the actual and processed images while the viewer moves and changes viewing angles. Areas of interest in the displayed image may be highlighted or include graphical information for the viewer.

Abstract translation: 一种使用相机22捕获输入图像的视觉信息系统，使用处理器28操纵图像，并且使用光学器件33投影处理的图像，以将经处理的图像叠加在由观看者观察的实际物体上。 处理是实时完成的，以便观众移动和改变观看角度时，观众可以同时看到实际和已处理的图像。 显示图像中的感兴趣区域可以被突出显示或包括用于观看者的图形信息。