公开(公告)号：US08193870B2

公开(公告)日：2012-06-05

申请号：US12838820

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03B7/12

CPC分类号： H03L7/0995 ,  H03L2207/06 ,  H03L2207/50

摘要： The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

摘要翻译： 本发明是用于补偿全数字锁相环中的频率牵引的方法和系统。 所有数字锁相环可以利用多相振荡器，其包括基本上所有锁存器与相应的虚拟单元配对的锁存器。 虚拟单元可以具有阻抗特性，例如对应于锁存器的可变电容值的可变电容值，使得即使参考时钟信号的极性改变，两个可变电容值的总和也保持基本恒定。 虚拟单元可以是例如可变电容器或虚拟锁存器。 锁相环也可以包括乘法单元。 乘法单元可以接收参考时钟信号并产生倍频参考时钟信号。

公开(公告)号：US20120013407A1

公开(公告)日：2012-01-19

申请号：US12838820

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03L7/00 ,  H03B19/14

CPC分类号： H03L7/0995 ,  H03L2207/06 ,  H03L2207/50

摘要： The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.

摘要翻译： 本发明是用于补偿全数字锁相环中的频率牵引的方法和系统。 所有数字锁相环可以利用多相振荡器，其包括基本上所有锁存器与相应的虚拟单元配对的锁存器。 虚拟单元可以具有阻抗特性，例如对应于锁存器的可变电容值的可变电容值，使得即使参考时钟信号的极性改变，两个可变电容值的总和也保持基本恒定。 虚拟单元可以是例如可变电容器或虚拟锁存器。 锁相环也可以包括乘法单元。 乘法单元可以接收参考时钟信号并产生倍频参考时钟信号。

公开(公告)号：US08222939B2

公开(公告)日：2012-07-17

申请号：US12838754

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： H03L7/06

CPC分类号： H03L7/16 ,  H03L2207/50

摘要： The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

摘要翻译： 本发明涉及一种全数字锁相环中毛刺校正的方法和系统。 全数字锁相环可以包括相位误差信号生成单元，多相位振荡器，毛刺校正单元和相位数字转换器。 相数转换器从多相振荡器接收多相信号并产生相位信号。 误差信号发生单元接收相位信号和参考相位信号，并产生馈送到毛刺校正单元的相位误差信号。 毛刺校正单元通过相位误差信号的一部分去除相位误差信号中的毛刺。 锁相环还可以包括相位旋转器和校准块。 校准块指示相位旋转器通过相位旋转旋转多相信号，该相位旋转产生最小数量的毛刺。

公开(公告)号：US20120013363A1

公开(公告)日：2012-01-19

申请号：US12838754

申请日：2010-07-19

申请人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

发明人： Koji Takinami ,  Richard Strandberg ,  Paul Cheng-Po Liang

IPC分类号： G01R29/02 ,  H03L7/06

CPC分类号： H03L7/16 ,  H03L2207/50

摘要： The present invention relates to a method and system for glitch correction in an all digital phase lock loop. An all digital phase lock loop can include a phase error signal generation unit, a multi-phase oscillator, a glitch correction unit, and a phase to digital converter. The phase to digital converter receives a multi-phase signal from the multi-phase oscillator and generates a phase signal. The error signal generation unit receives the phase signal and a reference phase signal and generates a phase error signal, which is fed to the glitch correction unit. The glitch correction unit removes the glitches in the phase error signal by a portion of the phase error signal. The phase lock loop can also include a phase rotator and a calibration block. The calibration block instructs the phase rotator to rotate the multi-phase signal by the phase rotation which generates the minimum number of glitches.

摘要翻译： 本发明涉及一种全数字锁相环中毛刺校正的方法和系统。 全数字锁相环可以包括相位误差信号生成单元，多相位振荡器，毛刺校正单元和相位数字转换器。 相数转换器从多相振荡器接收多相信号并产生相位信号。 误差信号生成单元接收相位信号和参考相位信号，并产生馈送到毛刺校正单元的相位误差信号。 毛刺校正单元通过相位误差信号的一部分去除相位误差信号中的毛刺。 锁相环还可以包括相位旋转器和校准块。 校准块指示相位旋转器通过相位旋转旋转多相信号，该相位旋转产生最小数量的毛刺。

公开(公告)号：US20070110184A1

公开(公告)日：2007-05-17

申请号：US11274068

申请日：2005-11-14

申请人： Paul Cheng-Po Liang ,  Richard Strandberg

发明人： Paul Cheng-Po Liang ,  Richard Strandberg

IPC分类号： H04L27/12

CPC分类号： H04L27/205

摘要： A device for transmitting information in a communications signal is envisioned. The information is modulated, at least in part, with a first angle-related characteristic. The device has a digital conversion circuit operable to convert information to be broadcast into a digital form. A constellation mapper is coupled to the digital conversion circuit, and is operable to convert the digital information into information associated with a constellation. A trajectory generation circuit generates samples denoting a trajectory within the constellation for the information. A transition analysis circuit determines a change in value of an angle-related characteristic in a transition between two samples, and a threshold detection circuit detects whether the change in value fails to meet a particular threshold. An angle-related characteristic distribution circuit can then distribute a portion of the change in value associated with the transition to at least one other transition.

摘要翻译： 设想在通信信号中发送信息的装置。 该信息至少部分地利用第一角度相关特征进行调制。 该装置具有数字转换电路，可操作以将待广播的信息转换为数字形式。 星座映射器耦合到数字转换电路，并且可操作以将数字信息转换为与星座相关联的信息。 轨迹生成电路生成表示信息星座内的轨迹的样本。 过渡分析电路确定两个采样之间的转换中的角度相关特性的值的变化，并且阈值检测电路检测值的变化是否不符合特定阈值。 角度相关特征分布电路然后可以将与转换相关联的值的变化的一部分分配给至少一个其他转变。