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    Method to implement flash memory
    1.
    发明授权
    Method to implement flash memory 有权
    实现闪存的方法

    公开(公告)号：US06285584B1

    公开(公告)日：2001-09-04

    申请号：US09769613

    申请日：2001-01-23

    申请人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

    发明人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

    IPC分类号： G11C1604

    CPC分类号： H01L27/11519 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

    摘要： A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

    摘要翻译： 公开了多个闪存电可擦除可编程只读存储器（EEPROM）单元，其中金属线耦合闪存单元的源极和漏极。 这些闪存单元的读取是通过向源极施加正电压并从相关联的金属源极线读取来实现的。 提供了用于增加过度编程的闪存单元的阈值电压的软擦除方案，其防止通过向漏极施加正电压而引起的泄漏。

    Method for operating flash memory
    2.
    发明授权
    Method for operating flash memory 有权
    操作闪存的方法

    公开(公告)号：US06212103B1

    公开(公告)日：2001-04-03

    申请号：US09363075

    申请日：1999-07-28

    申请人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

    发明人： Michael G. Ahrens ,  Anders T. Dejenfelt ,  Qi Lin ,  Robert A. Olah

    IPC分类号： G11C1604

    CPC分类号： H01L27/11519 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

    摘要： A plurality of flash electrically erasable programmable read only memory (EEPROM) cells is disclosed wherein metal lines couple both the sources and the drains of the flash cells. Reading of these flash cells is accomplished by applying a positive voltage to the source and reading from the associated metal source line. A soft erase scheme for increasing the threshold voltage of over-programmed flash cells is provided that prevents the leakage caused by applying a positive voltage to the drain.

    摘要翻译： 公开了多个闪存电可擦除可编程只读存储器（EEPROM）单元，其中金属线耦合闪存单元的源极和漏极。 这些闪存单元的读取是通过向源极施加正电压并从相关联的金属源极线读取来实现的。 提供了用于增加过度编程的闪存单元的阈值电压的软擦除方案，其防止通过向漏极施加正电压而引起的泄漏。

    Method of programming a three-terminal non-volatile memory element using source-drain bias
    3.
    发明授权
    Method of programming a three-terminal non-volatile memory element using source-drain bias 有权
    使用源极 - 漏极偏置来编程三端非易失性存储元件的方法

    公开(公告)号：US07420842B1

    公开(公告)日：2008-09-02

    申请号：US11210595

    申请日：2005-08-24

    申请人： Michael G. Ahrens ,  Shahin Toutounchi ,  James Karp ,  Jongheon Jeong

    发明人： Michael G. Ahrens ,  Shahin Toutounchi ,  James Karp ,  Jongheon Jeong

    IPC分类号： G11C11/34

    CPC分类号： G11C17/16 ,  G11C17/18

    摘要： A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

    摘要翻译： 存储晶体管通过在将编程电压施加到栅极的情况下偏置源极和漏极而被编程为非易失性存储器元件。 基板保持在与源极/漏极不同的电位，以确保在编程步骤期间在沟道区域和栅极之间而不是栅极和源极/漏极发生最大的电压差。 编程电压加热通道区域，以在源极和漏极之间形成非易失性低电阻连接，读取该电阻以确定编程状态。

    RAM-logic tile for field programmable gate arrays
    4.
    发明授权
    RAM-logic tile for field programmable gate arrays 失效
    用于现场可编程门阵列的RAM逻辑瓦

    公开(公告)号：US5465055A

    公开(公告)日：1995-11-07

    申请号：US325714

    申请日：1994-10-19

    申请人： Michael G. Ahrens

    发明人： Michael G. Ahrens

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/1736

    摘要： An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

    摘要翻译： 提出了一种用于现场可编程门阵列（FPGA）的改进的RAM逻辑瓦片（RLT）。 RLT位于全局水平和垂直线的交点处。 接线段在RLT之间本地运行，并包含用于连接RLT内的段和相邻RLT的可编程反熔丝。 RLT用传输门实现，并且可以有效地配置到存储器结构和/或逻辑器件中。

    Three-terminal non-volatile memory element with hybrid gate dielectric
    5.
    发明授权
    Three-terminal non-volatile memory element with hybrid gate dielectric 有权
    具有混合栅极电介质的三端非易失性存储元件

    公开(公告)号：US07687797B1

    公开(公告)日：2010-03-30

    申请号：US11210500

    申请日：2005-08-24

    申请人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

    发明人： James Karp ,  Daniel Gitlin ,  Shahin Toutounchi ,  Michael G. Ahrens ,  Jongheon Jeong

    IPC分类号： H01L29/06 ,  H01L47/02

    CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/11206

    摘要： A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

    摘要翻译： MOS晶体管用作可编程三端非易失性存储元件。 MOS晶体管的栅介质层具有比第二部分具有相对更高的介电击穿强度的第一部分。 选择第二部分的位置以避免在编程期间栅极电介质层在有源区域或隔离区域的边缘附近分解。 在特定实施例中，栅介质层是氧化硅，第一部分比第二部分厚。

    Switching circuit for transference of multiple negative voltages
    6.
    发明授权
    Switching circuit for transference of multiple negative voltages 有权
    用于多个负电压的转换的开关电路

    公开(公告)号：US06249458B1

    公开(公告)日：2001-06-19

    申请号：US09603462

    申请日：2000-06-22

    申请人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

    发明人： Farshid Shokouhi ,  Michael G. Ahrens ,  Ben Y. Sheen

    IPC分类号： G11C1600

    CPC分类号： G11C16/12 ,  G11C16/30

    摘要： A floating gate memory device that includes a switching circuit for selectively transferring two or more negative voltages to a common node (e.g., to the negative pole of a driver circuit). The switching circuit includes two switches respectively connected between the two negative voltages and the common node. Each of the switches includes series-connected triple-well NMOS transistors that provide a dual-isolation structure between the common node the negative voltage sources. An optional triple P-well resistor is provided between the series-connected triple-well NMOS transistors in each of the switches that includes a deep N-well region biased by a system voltage source (e.g., VCC) to reverse bias the central P-well region.

    摘要翻译： 一种浮动栅极存储器件，其包括用于选择性地将两个或更多个负电压传送到公共节点（例如，驱动电路的负极）的开关电路。 开关电路包括分别连接在两个负电压和公共节点之间的两个开关。 每个开关包括串联连接的三阱NMOS晶体管，其在公共节点之间提供负电压源之间的双重隔离结构。 在每个开关中的串联连接的三阱NMOS晶体管之间提供可选的三重P阱电阻器，其包括由系统电压源（例如VCC）偏置的深N阱区域，以反向偏置中心P- 井区。

    Ram-logic tile for field programmable gate arrays
    7.
    发明授权
    Ram-logic tile for field programmable gate arrays 失效
    用于现场可编程门阵列的Ram-logic瓦片

    公开(公告)号：US5629636A

    公开(公告)日：1997-05-13

    申请号：US521375

    申请日：1995-08-01

    申请人： Michael G. Ahrens

    发明人： Michael G. Ahrens

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/17728 ,  H03K19/1736

    摘要： An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

    摘要翻译： 提出了一种用于现场可编程门阵列（FPGA）的改进的RAM逻辑瓦片（RLT）。 RLT位于全局水平和垂直线的交点处。 接线段在RLT之间本地运行，并包含用于连接RLT内的段和相邻RLT的可编程反熔丝。 RLT用传输门实现，并且可以有效地配置到存储器结构和/或逻辑器件中。

    Programmable input/output buffer circuit with test capability
    8.
    发明授权
    Programmable input/output buffer circuit with test capability 失效
    具有测试能力的可编程输入/输出缓冲电路

    公开(公告)号：US5221865A

    公开(公告)日：1993-06-22

    申请号：US718677

    申请日：1991-06-21

    申请人： Christopher E. Phillips ,  Michael G. Ahrens ,  Joseph G. Nolan, III ,  Laurence H. Cooke

    发明人： Christopher E. Phillips ,  Michael G. Ahrens ,  Joseph G. Nolan, III ,  Laurence H. Cooke

    IPC分类号： G01R31/28 ,  H01L21/66 ,  H01L21/82 ,  H03K17/693 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/173

    CPC分类号： H03K17/693 ,  H03K19/00361 ,  H03K19/018585

    摘要： An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the first storing means for storing a signal from the first storing means, and a second multiplexer connected to an output terminal of the latch. The cells connected to each other and cells of other input/output buffer circuits from an output terminal of the flip-flop of one cell to a first input terminal of a first multiplexer of another cell for serial scanning of signals through the cells to test the system logic. Control lines are connected to the output terminals of the latch of the cells and to the decoding logic coupled to the programmable elements so that the programmable elements can be addressed for programming by serially scanning control signals through the cells.

    摘要翻译： 具有可编程元件的系统逻辑的集成电路，耦合到可编程元件的解码逻辑，用于寻址可编程元件;以及多个输入/输出缓冲电路，用于通过输入/输出端子在集成电路的系统逻辑与外部之间传递信号 被披露。 每个输入/输出缓冲电路包括具有连接到输入/输出端子的输出端的输出驱动级; 以及多个单元，每个单元具有多路复用器，连接到第一多路复用器的输出端的触发器，用于存储来自第一多路复用器的信号;锁存器，连接到第一存储装置的输出端，用于存储信号 以及连接到所述锁存器的输出端的第二多路复用器。 这些单元彼此连接，其它输入/输出缓冲电路的单元从一个单元的触发器的输出端子连接到另一个单元的第一多路复用器的第一输入端，用于通过单元串行扫描信号，以测试 系统逻辑。 控制线连接到单元的锁存器的输出端子和耦合到可编程元件的解码逻辑，使得可编程元件可以通过串行扫描通过单元的控制信号进行编程。