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    Methods, systems and media for functional simulation of noise and distortion on an I/O bus
    1.
    发明授权
    Methods, systems and media for functional simulation of noise and distortion on an I/O bus 有权
    在I / O总线上进行噪声和失真功能仿真的方法，系统和媒体

    公开(公告)号：US07246332B2

    公开(公告)日：2007-07-17

    申请号：US11053078

    申请日：2005-02-08

    申请人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  Robert James Reese ,  Chad Everett Winemiller

    发明人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  Robert James Reese ,  Chad Everett Winemiller

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

    摘要翻译： 公开了用于I / O总线的功能仿真的方法，系统和媒体。 更具体地，公开了一种模拟I / O总线的失真和噪声参数的方法。 实施例包括约束记录的一个或多个字段并且基于所得到的参数来确定延迟量，其中最终延迟量包括延迟缓冲器和与参数相关联的延迟量的净值。 实施例还可以包括确定要发送到I / O总线的下一位的值，并且在等待延迟量之后，将总线上的位驱动到下一个位值。 参数可能包括这些参数中的任何一个的偏移，抖动，占空比失真，电压参考失真和漂移。 另外的实施例可以包括响应于满足相位完成条件来发信号通知相位的结束。

    Verifying performance of a buffering and selection network device
    2.
    发明授权
    Verifying performance of a buffering and selection network device 失效
    验证缓冲和选择网络设备的性能

    公开(公告)号：US06643257B1

    公开(公告)日：2003-11-04

    申请号：US09478244

    申请日：2000-01-04

    申请人： Robert Brian Likovich, Jr. ,  Darryl Jonathan Rumph ,  Chad Everett Winemiller

    发明人： Robert Brian Likovich, Jr. ,  Darryl Jonathan Rumph ,  Chad Everett Winemiller

    IPC分类号： G01R3108

    CPC分类号： H04L1/24

    摘要： A method of and program for dynamically testing a buffering and selection device, wherein the buffering and selection device receives a transmission at an average bandwidth of T and in peak bandwidth bursts that may be greater than T, are provided. The buffering and selection device transmits data to one or more receive devices, all of which have a total average bandwidth of at least T. The buffering and selection device has buffers apportioned to each receive device in order to store data that is written in burst mode destined for that receive device. The method includes disabling the output data flow to the receive device being tested and then generating input data to the buffering and selection device tagged for each receive device in burst mode at a preselected number of transfers for each receive device. The program determines when the preselected number of transfers has occurred and then enables data flow to the receive device being tested. It is then determined if output to each receive device has commenced within a preselected latency period, and, if it has, it is determined if the preselected number of transfers of data has occurred within a preselected transfer period, i.e., meets bandwidth requirements.

    摘要翻译： 一种用于动态测试缓冲和选择设备的方法和程序，其中缓冲和选择设备以平均带宽T和可能大于T的峰值带宽突发接收传输。 缓冲和选择设备向一个或多个接收设备发送数据，所有接收设备都具有至少T的总平均带宽。缓冲和选择设备具有分配给每个接收设备的缓冲器，以便存储以突发模式写入的数据 注定接收设备。 该方法包括：禁止输出数据流到正被测试的接收设备，然后以每个接收设备的预先选择的传输次数，在突发模式下以每个接收设备标记的缓冲和选择设备生成输入数据。 该程序确定何时发生了预先选择的传输次数，然后使数据流向正在测试的接收设备。 然后，确定每个接收设备的输出是否在预先选择的等待时间段内已经开始，并且如果已经确定是否在预先选择的传送周期内已经发生了预先选择的数据传输数量，即满足带宽要求。

    Asynchronous data buffer and a method of use thereof
    4.
    发明授权
    Asynchronous data buffer and a method of use thereof 失效
    异步数据缓冲器及其使用方法

    公开(公告)号：US06876664B1

    公开(公告)日：2005-04-05

    申请号：US09541773

    申请日：2000-04-03

    申请人： Bryan Keith Bullis ,  John Charles Goss ,  Robert Brian Likovich, Jr.

    发明人： Bryan Keith Bullis ,  John Charles Goss ,  Robert Brian Likovich, Jr.

    IPC分类号： H04L12/56

    CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9063

    摘要： An improved asynchronous data buffer is disclosed. The data buffer comprises an entry section and a signaling circuit coupled to the entry section, the signaling circuit for signaling the data buffer to transfer a portion of a data cell from the entry section prior to the data cell being completely received by the entry section. Through the use of the data buffer in accordance with the present invention, data transfer systems are improved in two ways. Firsts by enabling data to be transferred before it is completely stored into the buffer, the latency that is typically required for data cell transfer is reduced. Second, the buffer storage space that is typically required to store a complete data cell is also reduced. This twofold improvement produces increased data transfer rates while decreasing the amount of required buffer storage space.

    摘要翻译： 公开了一种改进的异步数据缓冲器。 数据缓冲器包括一个入口部分和一个耦合到入口部分的信令电路，该信令电路用于在数据单元被入口部分完全接收之前，用于发信号通知数据缓冲器以从入口部分传输数据单元的一部分。 通过使用根据本发明的数据缓冲器，数据传输系统以两种方式被改进。 首先，在将数据完全存储到缓冲器之前，使数据能够传输，减少数据单元传输通常需要的延迟。 第二，通常需要存储完整数据单元的缓冲存储空间也减少了。 这种双重改进在减少所需缓冲存储空间的量的​​同时增加了数据传输速率。

    System and method to independently verify the execution rate of individual tasks by a device via simulation
    5.
    发明授权
    System and method to independently verify the execution rate of individual tasks by a device via simulation 失效
    系统和方法通过仿真独立地验证设备执行单个任务的执行率

    公开(公告)号：US06816829B1

    公开(公告)日：2004-11-09

    申请号：US09477163

    申请日：2000-01-04

    申请人： Robert Franklin Clark ,  Robert Brian Likovich, Jr. ,  Darryl Jonathan Rumph ,  Chad Everett Winemiller

    发明人： Robert Franklin Clark ,  Robert Brian Likovich, Jr. ,  Darryl Jonathan Rumph ,  Chad Everett Winemiller

    IPC分类号： G06F1310

    CPC分类号： G06F17/5022

    摘要： The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.

    摘要翻译： 本发明描述了一种通过仿真独立地验证设备执行速率的系统和方法。 描述了一种系统具有数据流向其他设备的主设备的情况。 巴士转车必须在所需费率之内。 该配置的模拟利用了各种设备的模型，包括“主设备”。 该模拟用于验证数据流量和相关传输速率。 数据传输包括随机突发，随机选择的脉冲间隔。 数据速率和数据有效性在每个脉冲串周期内被测量。

    Methods, systems and media for managing functional verification of a parameterizable design
    6.
    发明授权
    Methods, systems and media for managing functional verification of a parameterizable design 有权
    用于管理可参数设计的功能验证的方法，系统和媒体

    公开(公告)号：US07237210B2

    公开(公告)日：2007-06-26

    申请号：US11053220

    申请日：2005-02-08

    申请人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  David Otero ,  Chad Everett Winemiller

    发明人： Robert Brian Likovich, Jr. ,  Joseph David Mendenhall ,  John Christopher Morris ,  David Otero ,  Chad Everett Winemiller

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G01R31/318314

    摘要： Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.

    摘要翻译： 公开了用于管理可参数化设计的功能验证的方法，系统和媒体。 实施例包括具有测试台配置模块的系统，该测试台配置模块适于配置测试台，测试台具有测试台信号，以及具有多个通用设计端口的一个或多个实例组件，其中测试台信号被连接到多个端口。 测试台还可以具有基于芯片特定版本的设计的一个或多个实例化的特殊组件，其中特殊组件被连接到与通用设计相同的端口。 该系统还可以包括功能验证管理器，其通过组件模块观察测试台中的值并且基于所观察到的值自动配置验证环境，包括在不同层次结构中自动插入检查器。 在一些实施例中，测试台可以是VHDL或Verilog测试台。

    Semaphore management subsystem for use with multi-thread processor systems
    9.
    发明授权
    Semaphore management subsystem for use with multi-thread processor systems 失效
    用于多线程处理器系统的信号量管理子系统

    公开(公告)号：US07454753B2

    公开(公告)日：2008-11-18

    申请号：US10179860

    申请日：2002-06-25

    申请人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    发明人： Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

    IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F12/14 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G06F9/52

    摘要： A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

    摘要翻译： 用于在多线程处理系统中管理信号量的通用方法和装置具有用于处理系统中的每个线程的存储区域。 每个存储区域包括第一部分，用于存储用于从多线程处理系统使用的多个信号量中识别至少一个唯一信号量的至少一个标记，以及用于存储用于指示所存储的信号量的锁定状态的标记的第二部分 。 需要信号量的线程向信号量管理器发送信号锁定请求，该信号量管理器检查所有存储区域的内容，以确定所请求的信号量的状态。 如果请求的信号量未被锁定，则通过将请求的信号量和锁定状态插入到分配给请求线程的存储器位置中来锁定请求线程。