-
公开(公告)号：US5949272A
公开(公告)日：1999-09-07
申请号：US873830
申请日：1997-06-12
IPC分类号： H03K19/0185 , H03K17/62
CPC分类号： H03K19/018592 , H03K19/018585
摘要： A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.
摘要翻译： 提供了一种在芯片I / O缓冲多路复用器电路或I / O缓冲器单元201中实现的方法和装置.I / O缓冲器部分包括用于接收到缓冲芯片的总线输入信号的接收机电路205和 用于驱动从缓冲芯片到数据总线的输出信号的驱动器电路203。 集成多路复用器或MUX电路207有选择地将三个可能的信号之一门控到芯片内部逻辑。 施加到MUX电路的三个信号包括用于测试集成电路中的扫描点的边界扫描测试信号BS MUX，由芯片内部驱动逻辑产生的旁路数据输入信号DI和由I / O接收的DQ信号 数据总线缓冲接收电路。 I / O缓冲器的数据输入节点直接连接到新的多路复用器数据输入。 提供附加的控制信号用于三个多路复用器数据输入的正交选择。
-
2.发明授权Method of seamlessly integrating thermal event information data with performance monitor data 有权将热事件信息数据与性能监视数据无缝集成的方法公开(公告)号：US07472315B2
公开(公告)日：2008-12-30
申请号：US11054292
申请日：2005-02-09
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。
-
3.发明授权公开(公告)号：US07051177B2
公开(公告)日：2006-05-23
申请号：US10210359
申请日：2002-07-31
申请人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
发明人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
CPC分类号： G06F11/3466 , G06F11/3419 , G06F12/0897 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.
摘要翻译： 公开了一种用于确定分层存储器系统内特定级别的存储器的等待时间的方法。 分配性能监视计数器来计数负载数（负载计数器）和计数周期数（循环计数器）。 该方法开始于处理器确定要选择用于测量的负载。 响应于该确定，周期计数器值被存储在倒带寄存器中。 处理器发出负载并开始计数周期。 响应于负载完成，确定负载的存储器级别。 如果从期望的存储器级别执行负载，则负载计数器递增。 否则，循环计数器将重绕到其先前的值。
-
公开(公告)号：US07047398B2
公开(公告)日：2006-05-16
申请号：US10210358
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Michitaka Okuno , Masahiro Tokoro
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3865 , G06F11/3466 , G06F2201/88
摘要： A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.
摘要翻译： 一种用于识别计算机处理器中的一组指令的指令完成延迟的方法和系统。 指令组中的每个指令都有一个状态指示器，用于标识阻止该指令完成执行的内容。 完成延迟的示例是缓存未命中，数据依赖性或简单地计算机处理器中的执行单元处理指令所需的时间。 每个指令执行完毕后，相关状态指示灯将被清除，表示该指令不再等待执行。 执行的最后一条指令是保持整个组的完成的指令，因此将最后指令的完成延迟的原因记录为整个组的完成延迟的原因。
-
公开(公告)号：US06910120B2
公开(公告)日：2005-06-21
申请号：US10210357
申请日：2002-07-31
申请人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
发明人： Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Toshihiko Kurihara , Michitaka Okuno , Masahiro Tokoro
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.
摘要翻译： 公开了一种用于在推测性计算机微处理器内在性能监视计数器中维持正确值的电路和方法。 响应于确定微处理器内的推测执行开始，性能监视计数器的值被存储在倒带寄存器中。 性能监视计数器响应于预定事件递增。 如果微处理器确定推测执行不正确，倒带寄存器的值将被加载到计数器中，恢复计数器的正确值。
-
6.发明授权Pluggable electronic card presence detect scheme for use in parallel and serial vital detect product data (VPD) collection systems 失效用于并行和串行重要检测产品数据（VPD）收集系统的可插拔电子卡存在检测方案
公开(公告)号：US5953515A
公开(公告)日：1999-09-14
申请号：US837180
申请日：1997-04-11
CPC分类号： G06F13/4081
摘要： A vital product data (VPD) detection circuit mountable on a substrate of a pluggable component. The circuit comprises a "parallel read" circuit for generating vital product data associated with the pluggable component, a "serial read" circuit for storing and retrieving vital product data associated with the pluggable component, and means for interconnecting the parallel and serial read circuits. The parallel read circuit preferably comprises a parallel array of transistors surface-mounted on the substrate, and the serial read circuit preferably comprises a serial EEPROM having a clock input, a set of address inputs, and a bidirectional data pin. A VPD detection mechanism may disable the parallel VPD circuitry in favor of the serial VPD detection circuitry, or vice versa, or these circuits may be enabled but activated in a mutually exclusive manner.
摘要翻译： 安装在可插拔部件的基板上的重要产品数据（VPD）检测电路。 该电路包括用于产生与可插拔部件相关联的重要产品数据的“并行读取”电路，用于存储和检索与可插拔部件相关联的重要产品数据的“串行读取”电路，以及用于互连并行和串行读取电路的装置。 并行读取电路优选地包括表面安装在衬底上的晶体管的并行阵列，并且串行读取电路优选地包括具有时钟输入的串行EEPROM，一组地址输入和双向数据引脚。 VPD检测机制可以使并行VPD电路有利于串行VPD检测电路，反之亦然，或者这些电路可以被启用但以相互排斥的方式激活。
-
7.发明授权Method and apparatus for data ordering of I/O transfers in Bi-modal Endian PowerPC systems 失效用于双模式Endian PowerPC系统中I / O传输的数据排序的方法和装置
公开(公告)号：US5898896A
公开(公告)日：1999-04-27
申请号：US826853
申请日：1997-04-10
CPC分类号： G06F7/768 , G06F13/4013
摘要： To present a consistent image of storage facilities to components in Bi-modal Endian PowerPC system enviromnents, provision is made for transferring data between system components in the appropriate Endian format. Endian conversion function can be incorporated into the memory controller subsystem by adding byte-lane swapping logic on the inbound and outbound I/O data paths. With this structure, inbound data from the processor and memory bus will be converted to true Little Endian order before being sent to I/O devices. Likewise, true Little Endian data from I/O devices targeted for the processor or memory is modified to reflect the PowerPC Little Endian byte ordering convention.
摘要翻译： 为了向双模态Endian PowerPC系统环境中的组件呈现存储设施的一致形象，提供了以适当的Endian格式在系统组件之间传输数据。 通过在入站和出站I / O数据路径中添加字节通道交换逻辑，可以将端序转换功能并入内存控制器子系统。 利用这种结构，在发送到I / O设备之前，来自处理器和存储器总线的入站数据将被转换为真正的小端序。 同样，针对处理器或内存的I / O设备的真实小端数据也会被修改，以反映PowerPC小端字节排序规则。
-
8.发明授权Memory cards with symmetrical pinout for back-to-back mounting in computer system 失效具有对称引脚排列的存储卡，用于背靠背安装在计算机系统中公开(公告)号：US06202110B1
公开(公告)日：2001-03-13
申请号：US08829020
申请日：1997-03-31
IPC分类号： G06F1340
CPC分类号： G11C5/06 , G06F13/409 , G11C5/04 , H05K1/14
摘要： Memory cards for a computer system are placed back-to-back on an active backplane, using wiring topology where the memory address and data busses are wired to pairs of symmetrical connectors. This topology takes advantage of symmetrical memory card pinouts to improve memory bus performance while reducing backplane cost and wiring complexity. The symmetrical layout of the data and address wiring allows two memory cards to be placed back-to-back on the backplane, maintaining the same relative position of data and address pins between cards. Since the data and most of the address lines are common to each card, and any such data or (common or non-unique) address pin on one card can be wired to any other such data or address pin, respectively, on the other card, the back-to-back arrangement provides for minimal address and data bus interconnect lengths between connectors. Each data signal can be wired from a memory controller data pin on the first connector, then daisy-chained through the short printed circuit card wire to an adjacent pin on the second connector. Likewise, non-unique address pins can be connected from the memory controller to such address pins that are parallel between connectors. Those unique address and control signals which are to be connected together are placed as close as possible to the centerpoint of the edge connector.
摘要翻译： 计算机系统的存储卡使用布线拓扑将背板背对背放置在有源底板上，其中存储器地址和数据总线连接到成对的对称连接器。 该拓扑结构利用对称的存储卡引脚排列来改善内存总线性能，同时降低了背板的成本和布线的复杂性。 数据和地址布线的对称布局允许两个存储卡背对背地放置在背板上，保持卡之间的数据和地址引脚相同的相对位置。 由于数据和大多数地址线对于每个卡是共同的，并且一个卡上的任何这样的数据或（公共或非唯一）地址引脚可以分别连接到另一个卡上的任何其他这样的数据或地址引脚 ，背对背布置提供了连接器之间的最小地址和数据总线互连长度。 每个数据信号可以从第一个连接器上的存储器控制器数据引脚接线，然后通过短的印刷电路卡线菊花链连接到第二个连接器上的相邻引脚。 同样，非唯一地址引脚可以从存储器控制器连接到在连接器之间并行的这样的地址引脚。 要连接在一起的那些独特的地址和控制信号尽可能靠近边缘连接器的中心点。
-
9.发明授权Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters 失效使用多个分配的计数器计数指令表的等待时间，刷新，补充和指令执行公开(公告)号：US06970999B2
公开(公告)日：2005-11-29
申请号：US10210415
申请日：2002-07-31
申请人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
发明人： Toshihiko Kurihara , Hung Qui Le , Alexander Erik Mericas , Robert Dominick Mirabella , Hideki Mitsubayashi , Michitaka Okuno , Masahiro Tokoro
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/3855
摘要： A method and system for analyzing cycles per instruction (CPI) performance in a processor. A completion table corresponds to the instructions in a group to be processed by the processor. An empty completion table indicates that there has been some type of catastrophe that caused a table flush. While the table is empty, a performance monitoring counter (PMC), located in a performance monitoring unit (PMU) in the processor, counts the number of clock cycles that the table is empty. Preferably, a separate PMC is utilized depending on the reason that the completion table is empty. A second PMC likewise counts the number of clock cycles spent re-filling the empty completion table. A third PMC counts the number of clock cycles spent actually executing the instructions in the completion table. The information in the PMC's can be used to evaluate the true cause for degradation of CPI performance.
摘要翻译： 一种用于分析处理器中每条指令（CPI）性能的循环的方法和系统。 完成表对应于要由处理器处理的组中的指令。 一个空的完成表表明有一些类型的灾难导致表冲洗。 当表为空时，位于处理器中的性能监视单元（PMU）中的性能监视计数器（PMC）会计数表为空的时钟周期数。 优选地，根据完成表为空的原因，使用单独的PMC。 第二个PMC同样计算重新填充空完成表的时钟周期数。 第三个PMC计算在完成表中实际执行指令花费的时钟周期数。 PMC中的信息可用于评估CPI性能下降的真正原因。
-
10.发明授权Apparatus, system and computer program product for seamlessly integrating thermal event information data with performance monitor data 失效用于将热事件信息数据与性能监视数据无缝集成的装置，系统和计算机程序产品公开(公告)号：US07711994B2
公开(公告)日：2010-05-04
申请号：US12131070
申请日：2008-05-31
IPC分类号： G06F11/00
CPC分类号： G06F11/00
摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.
摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.017 秒)
