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公开(公告)号：US4291247A
公开(公告)日：1981-09-22
申请号：US77753
申请日：1979-09-21
IPC分类号： H03K19/017 , H03K19/096
CPC分类号： H03K19/0963 , H03K19/017 , H03K19/01728
摘要： Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.
摘要翻译： 特别是集成半导体类型的逻辑电路通过防止在访问时间期间发生上拉和通过包括片上延迟电路以避免以输出节点丢失信息的方式切换后续阶段而以改进的速度访问 的早期阶段很高。 响应于单个时钟脉冲边沿激活所有级。
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公开(公告)号：US4479216A
公开(公告)日：1984-10-23
申请号：US452157
申请日：1982-12-22
申请人： Robert H. Krambeck , Masakazu Shoji
发明人： Robert H. Krambeck , Masakazu Shoji
CPC分类号： H03K5/1565 , H03K5/133 , H03K2005/00195
摘要： An op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Any skew in the clock-in pulses results in a change in the average voltage of a clock-out pulse at the output of the arrangement. The average voltage of the clock-out pulse is compared to a reference voltage to produce a control signal which adjusts the average voltage at the output. Critical transitions in the clock pulses occur at precise time relationships under the control of the control signal.
摘要翻译： 运算放大器反馈装置用于提供来自偏斜时钟脉冲源的非偏斜时钟脉冲。 时钟输入脉冲中的任何偏移导致布置输出端的输出脉冲的平均电压发生变化。 将时钟输出脉冲的平均电压与参考电压进行比较，以产生调整输出端的平均电压的控制信号。 时钟脉冲中的临界转换在控制信号的控制下以精确的时间关系发生。
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公开(公告)号：US4396994A
公开(公告)日：1983-08-02
申请号：US221777
申请日：1980-12-31
申请人： Sung M. Kang , Robert H. Krambeck
发明人： Sung M. Kang , Robert H. Krambeck
CPC分类号： G06F9/30032 , G06F5/015 , G06F7/762
摘要： A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified. In addition, the circuit includes a network receiving data from the one-bit rotator and the shaft control word and rotating the data from the one-bit rotator in only the right direction by a magnitude specified by the shift control word. Furthermore, the circuit includes a plurality of output buffers receiving the data from the network and providing an output word.
摘要翻译： 用于在左右方向上旋转多位二进制字的电路包括：比例因子解码器，其接收指定旋转幅度的比例因子字，以及指定旋转方向的方向控制信号，并提供移位控制字 当指定正确的旋转时，它与比例因子字相同，但是当指定左旋转时提供作为缩放因子字的补码的移位控制字。 该电路还包括接收输入字并提供相应输入数据的多个输入缓冲器，以及接收输入数据和方向控制信号的一位旋转器，并且当左旋转时将输入数据向右方向旋转一个位置 在指定正确的旋转时被指定或提供输入数据而不旋转。 此外，电路包括从一位旋转器和轴控制字接收数据的网络，并且将来自一位旋转器的数据仅沿右方向旋转由换档控制字指定的幅度。 此外，电路包括从网络接收数据并提供输出字的多个输出缓冲器。
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公开(公告)号：US4189716A
公开(公告)日：1980-02-19
申请号：US969705
申请日：1978-12-15
申请人： Robert H. Krambeck
发明人： Robert H. Krambeck
CPC分类号： G06F7/607
摘要： The numbers of gates necessary in an integrated combinatorial logic circuit is reduced by designing the circuit to accept an applied binary word of given length as a plurality of word segments having numbers of bits which add up to the number included in the applied word. A preprocessor responds to the word segments to generate a word characterizing the segments and to apply those words to an arithmetic logic unit designed to add binary words and to generate words having lengths of the applied words.
摘要翻译： 集成组合逻辑电路中必需的门数通过将电路设计为接受给定长度的应用二进制字作为多个字段而减少，所述多个字段具有与所应用的字中包含的数目相加的位数。 预处理器响应于单词段以生成表征段的单词并将这些单词应用于被设计为添加二进制单词并且生成具有所应用单词长度的单词的算术逻辑单元。
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公开(公告)号：USRE33664E
公开(公告)日：1991-08-13
申请号：US397342
申请日：1989-08-22
申请人： Sung M. Kang , Robert H. Krambeck , Alfred Y. Kwan
发明人： Sung M. Kang , Robert H. Krambeck , Alfred Y. Kwan
CPC分类号： G06F9/30032 , G06F5/015
摘要： .[.A circuit for rotating a multibit binary word in either the right or the left direction includes a scale factor decoder receiving a scale factor word which specifies the magnitude of the rotation and a direction control signal which specifies the direction of rotation and providing a shift control word which is the same as the scale factor word when a right rotation is specified but providing a shift control word which is the complement of the scale factor word when a left rotation is specified. The circuit also includes a plurality of input buffers receiving an input word and providing corresponding input data, and a one-bit rotator receiving the input data and the direction control signal and rotating the input data in the right direction by one position when a left rotation is specified or providing the input data without rotation when a right rotation is specified. In addition, the circuit includes a network receiving data from the one-bit rotator and the shaft control word and rotating the data from the one-bit rotator in only the right direction by a magnitude specified by the shift control word. Furthermore, the circuit includes a plurality of output buffers receiving the data from the network and providing an output word..]..Iadd.A data shift/rotate circuit is designed to have the capability of either shifting or rotating data by a number of bit positions prescribed by an input word. The shifting vs. rotating is selected by a binary digital rotate control signal (ROT). The shifting or rotating can be either to the right or to the left, depending upon a binary digital direction control signal (L/R). .Iaddend.
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