公开(公告)号：US4139907A

公开(公告)日：1979-02-13

申请号：US829570

申请日：1977-08-31

Applicant: Donald E. Blahut ,  James A. Cooper, Jr.

Inventor： Donald E. Blahut ,  James A. Cooper, Jr.

IPC: G11C17/00 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C11/40

CPC classification number: G11C17/12 ,  H01L27/112

Abstract: The word conductors of a semiconductor integrated ROM are foreshortened where permitted by the organization of data in the memory. The space made available by the eliminated portions of the word conductors is used for electrical connection to the bit conductors from the sides of the array rather than at the ends. A space reduction of about thirty percent is achieved.

Abstract translation: {PG，1半导体集成ROM的字导体在存储器中的数据组织允许的情况下被缩短。 由字导体的消除部分提供的空间用于从阵列的侧面而不是端部与位导体电连接。 实现了大约30％的空间减少。

公开(公告)号：US4324038A

公开(公告)日：1982-04-13

申请号：US209755

申请日：1980-11-24

Applicant: Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

Inventor： Chuan C. Chang ,  James A. Cooper, Jr. ,  Dawon Kahng ,  Shyam P. Murarka

IPC: H01L21/285 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66621 ,  H01L21/28537 ,  H01L29/66643 ,  H01L29/7839

Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).

Abstract translation: 在半导体本体（10）中制造MOSFET器件（20）的方法包括在栅极氧化物（10.3）生长之前和形成高电导率表面之后形成源极和漏极接触电极（12.1,12.2）的步骤 地区（10.5）。 每个接触电极（12.1,12.2）的暴露的相互相对的侧壁边缘被涂覆有侧壁二氧化硅层（15.1,15.2），并且将这些侧壁之间的半导体本体（10）的暴露的表面蚀刻到深度 在高导电性表面区域（10.5）之下，以将其分离成源极和漏极区域（10.1,10.2）。 通过使用用于接触电极（12.1,12.2）的肖特基势垒或杂质掺杂材料，可以省略高导电性区域的形成。

公开(公告)号：US5465249A

公开(公告)日：1995-11-07

申请号：US798219

申请日：1991-11-26

Applicant: James A. Cooper, Jr. ,  John W. Palmour ,  Calvin H. Carter, Jr.

Inventor： James A. Cooper, Jr. ,  John W. Palmour ,  Calvin H. Carter, Jr.

IPC: G11C14/00 ,  G11C11/404 ,  G11C17/00 ,  H01L21/8229 ,  H01L21/8246 ,  H01L27/102 ,  H01L27/105 ,  H01L29/24 ,  G11C11/401

CPC classification number: H01L29/1608 ,  G11C11/404 ,  H01L27/1023

Abstract: A random access memory (RAM) cell in 6H-SiC having storage times when all bias is removed long enough to be considered nonvolatile. The nonvolatile random access memory (NVRAM) cell comprises a bit line, a charge storage device in silicon carbide, and a transistor in silicon carbide connecting the charge storage device to the bit line. The bipolar NVRAM cell has a bipolar transistor with a base region, an emitter region, and a floating collector region, wherein the charge storage device in the bipolar NVRAM is a p-n junction adjacent the floating collector region of the cell. The metal-oxide-semiconductor (MOS) NVRAM has a MOS field effect transistor (MOSFET) with a channel region, a source region, and a drain region, wherein the charge storage device in the MOS NVRAM is a MOS capacitor adjacent the drain region of the MOSFET.

Abstract translation: 6H-SiC中的随机存取存储器（RAM）单元具有所有偏移被去除的存储时间，足以被认为是非易失性的。 非易失性随机存取存储器（NVRAM）单元包括位线，碳化硅中的电荷存储装置和将电荷存储装置连接到位线的碳化硅晶体管。 双极NVRAM单元具有双极晶体管，其具有基极区域，发射极区域和浮动集电极区域，其中双极NVRAM中的电荷存储器件是邻近电池的浮置集电极区域的p-n结。 金属氧化物半导体（MOS）NVRAM具有沟道区，源极区和漏极区的MOS场效应晶体管（MOSFET），其中MOS NVRAM中的电荷存储装置是与漏极区相邻的MOS电容 的MOSFET。

公开(公告)号：US4894689A

公开(公告)日：1990-01-16

申请号：US687127

申请日：1984-12-28

Applicant: James A. Cooper, Jr. ,  Karvel K. Thornber

Inventor： James A. Cooper, Jr. ,  Karvel K. Thornber

IPC: H01L29/78 ,  H01L47/00 ,  H01L47/02

CPC classification number: H01L47/02

Abstract: A transferred electron device is described in which the charge of the drifting packets is imaged perpendicular to the charge-packet direction so that essentially all of the packet-averaged, space-charge field is normal to the drift direction. This permits continuous formation of contiguous charge packets.

Abstract translation: 描述了转移的电子器件，其中漂移包的电荷垂直于电荷包方向成像，使得基本上所有的分组平均的空间电荷场垂直于漂移方向。 这允许连续形成连续的电荷包。

公开(公告)号：US4719496A

公开(公告)日：1988-01-12

申请号：US631041

申请日：1986-02-12

Applicant: Federico Capasso ,  James A. Cooper, Jr. ,  Karvel K. Thornber

Inventor： Federico Capasso ,  James A. Cooper, Jr. ,  Karvel K. Thornber

IPC: H01L29/10 ,  H01L29/15 ,  H01L29/36 ,  H01L29/861 ,  H01L45/00 ,  H01L29/205

CPC classification number: H01L29/157 ,  H01L29/1029 ,  H01L29/155 ,  H01L29/365 ,  H01L29/8618

Abstract: Semiconductor structures suitable for repeated velocity overshoot are described. The structure comprises at least two velocity overshoot sections with each section comprising a first semiconductor region having a rapid change in potential and a dimension such that the carrier transit time is comparable to or shorter than the mean scattering time and a second semiconductor region having a more gradual change in potential and a dimension such that the carrier transit time is sufficient to allow the energy relaxation time to be exceeded.

Abstract translation: 描述适用于重复速度超调的半导体结构。 该结构包括至少两个速度过冲部分，每个部分包括具有快速变化的电位的第一半导体区域和使得载流子渡越时间与平均散射时间相当或更短的尺寸，以及具有更多的第二半导体区域 电势的逐渐变化和使得载流子传播时间足以允许超过能量松弛时间的尺寸。

公开(公告)号：US06362495B1

公开(公告)日：2002-03-26

申请号：US09264156

申请日：1999-03-05

Applicant: Kipp J. Schoen ,  Jason P. Henning ,  Jerry M. Woodall ,  James A. Cooper, Jr. ,  Michael R. Melloch

Inventor： Kipp J. Schoen ,  Jason P. Henning ,  Jerry M. Woodall ,  James A. Cooper, Jr. ,  Michael R. Melloch

IPC: H01L310312

CPC classification number: H01L29/1608 ,  H01L29/47 ,  H01L29/872 ,  H01L31/0312

Abstract: A dual-metal-trench silicon carbide Schottky pinch rectifier having a plurality of trenches formed in an n-type SiC substrate, with a Schottky contact having a relatively low barrier height on a mesa defined between adjacent ones of the trenches, and a Schottky contact having a relatively high barrier height at the bottom of each trench. The same metal used for the Schottky contact in each trench is deposited over the Schottky contact on the mesa. A simplified fabrication process is disclosed in which the high barrier height metal is deposited over the low barrier height metal and then used as an etch mask for reactive ion etching of the trenches to produce a self-aligned low barrier contact.

Abstract translation: 一种双金属沟槽碳化硅肖特基压紧整流器，其具有形成在n型SiC衬底中的多个沟槽，肖特基接触在相邻沟槽之间限定的台面上具有相对较低的势垒高度，以及肖特基接触 在每个沟槽的底部具有较高的势垒高度。 在每个沟槽中用于肖特基接触的相同金属沉积在台面上的肖特基接触件上。 公开了一种简化的制造工艺，其中高阻挡高度金属沉积在低阻挡高度金属上，然后用作蚀刻掩模以用于沟槽的反应离子蚀刻以产生自对准低阻挡接触。

公开(公告)号：US5365477A

公开(公告)日：1994-11-15

申请号：US899538

申请日：1992-06-16

Applicant: James A. Cooper, Jr. ,  Michael R. Melloch ,  Theresa B. Stellwag

Inventor： James A. Cooper, Jr. ,  Michael R. Melloch ,  Theresa B. Stellwag

IPC: H01L27/06 ,  H01L27/102 ,  H01L29/92 ,  H01L29/161

CPC classification number: H01L27/0605 ,  H01L27/1023 ,  H01L29/92

Abstract: A vertically integrated DRAM cell having a storage time of at least 4.5 hours at room temperature, formed from a wide-bandgap semiconductor such as GaAs or AlGaAs, in which an n-p-n bipolar access transistor is merged with a p-n-p storage capacitor, with the middle p-n layers being common to both. Similarly, a p-n-p transistor can be merged with an n-p-n storage capacitor.

Abstract translation: 由GaAs或AlGaAs等宽带隙半导体形成的室温下至少4.5小时的垂直集成DRAM单元，其中npn双极存取晶体管与pnp存储电容器合并，中间pn 两层都是共同的。 类似地，p-n-p晶体管可以与n-p-n存储电容器合并。

公开(公告)号：US4635083A

公开(公告)日：1987-01-06

申请号：US851273

申请日：1986-04-10

Applicant: James A. Cooper, Jr.

Inventor： James A. Cooper, Jr.

IPC: H01L27/06 ,  H01L27/108 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/108 ,  H01L27/0605

Abstract: A memory device includes a relative lower bandgap energy first semiconductor layer, a relatively higher bandgap energy second semiconductor layer on the first, an alloy source rectifying to the first layer, a well for storing charge and a gate for controlling charge flow between the source and the well. The gate is formed on the second layer, as is a field plate for controlling the storage charge in the well. In one embodiment, a buried channel field effect transistor is combined with the basic memory device, with the charge content of the well controlling current flow between the source and drain of the buried channel FET.

Abstract translation: 存储器件包括相对较低的带隙能量第一半导体层，第一相对较高的带隙能量第二半导体层，对第一层整流的合金源，用于存储电荷的阱和用于控制源极和 那个井 栅极形成在第二层上，栅极板也用于控制井中的储存电荷。 在一个实施例中，掩埋沟道场效应晶体管与基本存储器件组合，阱控制电流的电荷含量在掩埋沟道FET的源极和漏极之间流动。

公开(公告)号：US4291247A

公开(公告)日：1981-09-22

申请号：US77753

申请日：1979-09-21

Applicant: James A. Cooper, Jr. ,  Robert H. Krambeck

Inventor： James A. Cooper, Jr. ,  Robert H. Krambeck

IPC: H03K19/017 ,  H03K19/096

CPC classification number: H03K19/0963 ,  H03K19/017 ,  H03K19/01728

Abstract: Logic circuits, particularly of the integrated semiconductor type, are accessed at improved speeds by preventing pull-ups from occurring during the access time and by the inclusion of on-chip delay circuitry to avoid switching later stages in a manner to lose information while output nodes of earlier stages are high. All stages are activated in response to a single clock pulse edge.

Abstract translation: 特别是集成半导体类型的逻辑电路通过防止在访问时间期间发生上拉和通过包括片上延迟电路以避免以输出节点丢失信息的方式切换后续阶段而以改进的速度访问 的早期阶段很高。 响应于单个时钟脉冲边沿激活所有级。

公开(公告)号：US4208728A

公开(公告)日：1980-06-17

申请号：US971866

申请日：1978-12-21

Applicant: Donald E. Blahut ,  James A. Cooper, Jr.

Inventor： Donald E. Blahut ,  James A. Cooper, Jr.

IPC: H03K19/177 ,  G11C11/40

CPC classification number: H03K19/1772

Abstract: The decoder portion of a programable logic array (PLA) includes logic devices at crosspoints defined between the word (x) lines and the address (y) lines characteristic of a decoder portion. The devices are operative to combine two or more word lines to activate a single word line in the associated read only memory (ROM) in response to one of two or more possible inputs. The technique is effective even in cases where "don't care" conditions relating the two or more possible inputs cannot be found. A substantial reduction in chip area is achieved.

Abstract translation: 可编程逻辑阵列（PLA）的解码器部分包括在解码器部分的字（x）线和地址（y）线特性之间定义的交叉点处的逻辑器件。 这些装置可操作以组合两个或更多个字线，以响应于两个或多个可能输入中的一个来激活相关联的只读存储器（ROM）中的单个字线。 即使在“无关”条件下，无法找到两个或多个可能输入的情况，该技术也是有效的。 实现了芯片面积的显着降低。