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公开(公告)号：US06781911B2
公开(公告)日：2004-08-24
申请号：US10119919
申请日：2002-04-09
申请人： Robert J. Riesenman , James M. Dodd
发明人： Robert J. Riesenman , James M. Dodd
IPC分类号： G11C700
CPC分类号： G11C5/143 , G11C7/20 , G11C11/4072
摘要： Methods and devices for a memory system are disclosed. A digital memory device can receive power-down commands during the pendency of an active-mode command such as a burst read or write, that is, “early”. The device shuts down some circuitry, such as address and command registers, immediately upon receipt of the early power-down command. Other device components, e.g., those involved in servicing the burst read or write, remain active at least until their portion of the command has been completed. In some embodiments, the early power-down command can be issued concurrently with an active-mode command as an option to that command, freeing a memory controller from having to schedule and issue power-down commands separately. Significant power savings, as compared to those obtained with prior-art memory device power-down modes, are possible.
摘要翻译： 公开了用于存储器系统的方法和装置。 数字存储设备可以在诸如突发读或写之类的活动模式命令（即“早”）的等待期间接收掉电命令。 该设备在收到早期停电命令后立即关闭某些电路，如地址和命令寄存器。 其他设备组件，例如涉及服务突发读或写操作的设备组件至少直到其命令的部分已经完成为止。 在一些实施例中，早期掉电命令可以与作为该命令的选项的主动模式命令同时发出，释放存储器控制器不必分别调度和发布掉电命令。 与使用现有技术的存储器件掉电模式获得的功率相比，显着的功率节省是可能的。
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2.发明授权公开(公告)号：US06747912B1
公开(公告)日：2004-06-08
申请号：US10334809
申请日：2002-12-31
申请人： Robert J. Riesenman
发明人： Robert J. Riesenman
IPC分类号： G11C818
CPC分类号： G06F13/4077 , G06F13/1689
摘要： A combination precharge/activate command is utilized in order to make more efficient use of a command bus between a memory controller and a system memory. Upon receiving a precharge/activate command from the memory controller, the system memory makes a determination as to how to interpret the command depending on a page status. For an open page, the precharge/activate command is treated as a precharge command and then the system memory performs an activate with proper command timing using address and bank given during precharge/activate command. For a closed page, the precharge/activate command is treated as an activate command.
摘要翻译： 使用组合预充电/激活命令以便更有效地使用存储器控制器和系统存储器之间的命令总线。 在从存储器控制器接收到预充电/激活命令时，系统存储器确定如何根据页面状态来解释命令。 对于打开的页面，预充电/激活命令被视为预充电命令，然后系统存储器使用预充电/激活命令中给定的地址和存储器，以适当的命令定时来执行激活。 对于闭合页面，预充电/激活命令被视为激活命令。
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3.发明授权Method and apparatus for terminating a bus transaction if the target is not ready 失效如果目标未准备就终止总线事务的方法和装置公开(公告)号：US06275887B1
公开(公告)日：2001-08-14
申请号：US09271616
申请日：1999-03-17
IPC分类号： G06F1336
CPC分类号： G06F13/4226 , G06F13/36
摘要： One embodiment of the present invention is a PCI bus target device. The PCI bus target device includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to determine whether the PCI bus target device is the target of a first transaction initiated by a first PCI bus master device. The second circuit is configured to determine whether the PCI bus target device is ready to complete the first transaction. The third circuit is configured to determine whether a second PCI bus master device is ready to initiate a second transaction. The fourth circuit is configured to terminate the first transaction if the PCI bus target device is the target of the first transaction and is not ready to complete the first transaction and the second PCI bus master device is ready to initiate the second transaction.
摘要翻译： 本发明的一个实施例是PCI总线目标设备。 PCI总线目标器件包括第一电路，第二电路，第三电路和第四电路。 第一电路被配置为确定PCI总线目标设备是否是由第一PCI总线主设备发起的第一事务的目标。 第二电路被配置为确定PCI总线目标设备是否准备好完成第一次交易。 第三电路被配置为确定第二PCI总线主设备是否准备好发起第二事务。 第四电路被配置为如果PCI总线目标设备是第一事务的目标并且不准备完成第一事务并且第二PCI总线主设备准备启动第二事务，则终止第一事务。
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公开(公告)号：US06957307B2
公开(公告)日：2005-10-18
申请号：US10104412
申请日：2002-03-22
CPC分类号： G06F13/1668
摘要： A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.
摘要翻译： 存储器控制器或其他设备可以用数据掩模映射方案来编程。 存储器控制器内的选择设备可以用数据掩码映射方案设置在数据和数据掩码之间。 在一个实施例中，可以使用数据掩模映射方案来包含存储设备并对其进行编程。
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公开(公告)号：US06952367B2
公开(公告)日：2005-10-04
申请号：US10701025
申请日：2003-11-03
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
摘要翻译： 数据掩模图可以以各种方式编程到存储设备中。 在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。 在另一个实施例中，从存储器中的位置检索数据掩码图。 在另一个实施例中，通过算法确定数据掩码图。
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公开(公告)号：US06801459B2
公开(公告)日：2004-10-05
申请号：US10104837
申请日：2002-03-22
IPC分类号： G11C1604
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
摘要翻译： 数据掩模图可以以各种方式编程到存储设备中。 在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。 在另一个实施例中，从存储器中的位置检索数据掩码图。 在另一个实施例中，通过算法确定数据掩码图。
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公开(公告)号：US06925013B2
公开(公告)日：2005-08-02
申请号：US10786940
申请日：2004-02-24
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
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8.发明授权System for delaying dequeue of commands received prior to fence command until commands received before fence command are ordered for execution in a fixed sequence 失效用于延迟在fence命令之前接收到的命令的出队系统，直到在fence命令之前接收到的命令被按顺序执行为止
公开(公告)号：US6047334A
公开(公告)日：2000-04-04
申请号：US877126
申请日：1997-06-17
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for fencing the execution of commands. A fence command and an executable command are received in succession. The executable command is enqueued in a first queue together with an indication that the executable command succeeded the fence command. A synchronization value is enqueued in a second queue. The executable command is then delayed from being dequeued from the first queue until the synchronization value is advanced to the head of the second queue.
摘要翻译： 一种防止命令执行的方法和装置。 接收到fence命令和可执行命令。 可执行命令与第一个队列一起排队，以及可执行命令成功执行fence命令的指示。 同步值在第二个队列中排队。 然后可执行命令被延迟从第一队列出队，直到同步值前进到第二队列的头。
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9.发明授权System for issuing a command to a memory having a reorder module for priority commands and an arbiter tracking address of recently issued command 失效用于向具有用于优先级命令的重新排序模块的存储器发出命令的系统和最近发出的命令的仲裁器跟踪地址的系统
公开(公告)号：US6112265A
公开(公告)日：2000-08-29
申请号：US835388
申请日：1997-04-07
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0674
摘要： A system and method is provided for enhancing the efficiency with which commands from and initiating device to a resource are processed by the resource. The system includes a command queue, a plurality of command reorder slots coupled to the command queue, and command selection logic coupled to the resource and the command reorder slots. Commands ready for processing are loaded into the command reorder slots, and the command selection logic applies an efficiency criterion to the loaded commands. A command meeting the efficiency criterion is transferred to the resource for processing. The system may also include response reordering logic, which is coupled to the command reorder logic. The response reorder logic returns to original command order data provided in response to reorder read commands.
摘要翻译： 提供了一种系统和方法，用于提高由资源处理来自设备到资源的命令的效率。 系统包括命令队列，耦合到命令队列的多个命令重新排序时隙，以及耦合到资源和命令重新排序时隙的命令选择逻辑。 准备处理的命令被加载到命令重新排序槽中，并且命令选择逻辑对加载的命令应用效率标准。 满足效率标准的指令被转移到资源进行处理。 系统还可以包括响应重排序逻辑，其被耦合到命令重排序逻辑。 响应重新排序逻辑返回到响应于重新排序读取命令提供的原始命令顺序数据。
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10.发明授权Method and apparatus for avoiding deadlock in the issuance of commands that are reordered and require data movement according to an original command order 失效用于在重新排序并根据原始命令顺序需要数据移动的命令的发布中避免死锁的方法和装置
公开(公告)号：US5974571A
公开(公告)日：1999-10-26
申请号：US941886
申请日：1997-09-30
CPC分类号： G06F13/1626 , G06F13/4036
摘要： A method of issuing a data retrieval command to a re-order unit in a bus bridge is described. The method requires maintaining an indication of the available (or unreserved) capacity in a data buffer into which a data package is received from a memory resource in response to a data retrieval command. Data packages are furthermore dispatched, relative to other data packages, in the order in which a corresponding data retrieval command is issued from a requesting device. The size of a data package requested by each data retrieval command is determined prior to issuance thereof to the re-order unit. The size of each data package is then compared to the then available capacity in the data buffer, and the relevant data retrieval command is only issued to the re-order unit if the available capacity in the data buffer is sufficient to accommodate the data package requested by the relevant data retrieval command.
摘要翻译： 描述了向总线桥中的重新排序单元发出数据检索命令的方法。 该方法需要响应于数据检索命令，保持从存储器资源接收数据包的数据缓冲器中的可用（或未保留）容量的指示。 数据包相对于其他数据包，按照从请求设备发出相应的数据检索命令的顺序进行调度。 每个数据检索命令请求的数据包的大小在发布到重新排序单元之前被确定。 然后将每个数据包的大小与数据缓冲区中的当前可用容量进行比较，并且如果数据缓冲器中的可用容量足以容纳请求的数据包，则相关数据检索命令仅发送到重新排序单元 通过相关数据检索命令。
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