公开(公告)号：US07523230B1

公开(公告)日：2009-04-21

申请号：US11137314

申请日：2005-05-24

Applicant: James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

Inventor： James M. Dodd ,  Brian P. Johnson ,  Jay C. Wells ,  John B. Halbert

IPC: G06F13/28 ,  G06F13/00 ,  G06F13/14 ,  G06F3/00 ,  G06F12/00

CPC classification number: G06F13/1668 ,  G11C7/1027 ,  G11C7/1066 ,  G11C7/1072

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract translation: 本发明包括一种用于控制在存储器件上执行的读和写操作的数据长度的方法和装置。 该方法包括确定可操作地耦合到存储器件的存储器控​​制器可用的第一数量的通道; 确定填充频道的数量的第二数字代表; 基于第一和第二数字计算突发长度; 并且对存储器控制器进行编程以使用突发长度作为在存储器件上执行的读和写操作的数据长度。

公开(公告)号：US07404047B2

公开(公告)日：2008-07-22

申请号：US10446986

申请日：2003-05-27

Applicant: James M. Dodd ,  Robert Milstrey

Inventor： James M. Dodd ,  Robert Milstrey

IPC: G06F13/14

CPC classification number: G06F13/1631

Abstract: Methods and apparatuses for improving processor performance in a multi-processor system by optimizing accesses to memory. Processors can track the state of a memory such that the memory can be efficiently utilized in a multi-processor system including the ability to decode incoming snoop addresses from other processors, comparing them to contents of a memory tracking register(s), and updating tracking register(s) appropriately. Likewise, the transactions from other non-processor bus agents and/or bus mastering devices, such as a bus bridge, memory controller, Input/output (I/O), and graphics could also be tracked.

Abstract translation: 通过优化对存储器的访问来提高多处理器系统中处理器性能的方法和装置。 处理器可以跟踪存储器的状态，使得可以在多处理器系统中有效地利用存储器，包括从其他处理器解码输入的窥探地址的能力，将它们与存储器跟踪寄存器的内容进行比较，以及更新跟踪 注册适当。 同样，也可以跟踪来自其他非处理器总线代理和/或总线主控设备（诸如总线桥，存储器控制器，输入/输出（I / O）和图形）的事务。

公开(公告)号：US07076617B2

公开(公告)日：2006-07-11

申请号：US10676781

申请日：2003-09-30

Applicant: James M. Dodd

Inventor： James M. Dodd

IPC: G06F12/00

CPC classification number: G06F12/0215

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a memory controller of a processor and/or chipset may adaptively determine whether to close pages of a memory in an attempt to increase perceived memory performance.

Abstract translation: 描述了处理存储器事务的机器可读介质，方法和装置。 在一些实施例中，处理器和/或芯片组的存储器控​​制器可以自适应地确定是否关闭存储器的页面以试图增加感知的存储器性能。

公开(公告)号：US06957307B2

公开(公告)日：2005-10-18

申请号：US10104412

申请日：2002-03-22

Applicant: Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

Inventor： Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

IPC: G06F13/16 ,  G06F12/00

CPC classification number: G06F13/1668

Abstract: A memory controller or other device may be programmed with a data mask mapping scheme. A selection device within the memory controller may be set with the data mask mapping scheme between data and a data mask. In one embodiment, a storage device may be included and programmed with the data mask mapping scheme.

Abstract translation: 存储器控制器或其他设备可以用数据掩模映射方案来编程。 存储器控制器内的选择设备可以用数据掩码映射方案设置在数据和数据掩码之间。 在一个实施例中，可以使用数据掩模映射方案来包含存储设备并对其进行编程。

公开(公告)号：US06952367B2

公开(公告)日：2005-10-04

申请号：US10701025

申请日：2003-11-03

Applicant: Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

Inventor： Robert J. Riesenman ,  James M. Dodd ,  Michael W. Williams

IPC: G06F12/04 ,  G06F12/06 ,  G06F13/16 ,  G11C16/04

CPC classification number: G06F13/1626 ,  G06F12/04

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract translation: 数据掩模图可以以各种方式编程到存储设备中。 在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。 在另一个实施例中，从存储器中的位置检索数据掩码图。 在另一个实施例中，通过算法确定数据掩码图。

公开(公告)号：US06888777B2

公开(公告)日：2005-05-03

申请号：US10229617

申请日：2002-08-27

Applicant: James M. Dodd ,  Robert Milstrey

Inventor： James M. Dodd ,  Robert Milstrey

IPC: G06F12/06 ,  G11C8/00

CPC classification number: G06F12/06

Abstract: Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory with the processor decoded address without decoding the address itself. In other embodiments, a processor or other external components provide a memory controller with partially decoded memory addresses. The memory controller then generates a decoded address from the partially decoded address and may access the memory with the generated decoded address.

Abstract translation: 描述了处理存储器事务的机器可读介质，方法和装置。 在一些实施例中，处理器或其它外部组件向存储器控制器提供经解码的存储器地址。 然后，存储器控制器可以利用处理器解码的地址访问存储器，而不解码地址本身。 在其他实施例中，处理器或其他外部组件为存储器控制器提供部分解码的存储器地址。 存储器控制器然后从部分解码的地址生成解码的地址，并且可以利用所生成的解码地址访问存储器。

公开(公告)号：US06862653B1

公开(公告)日：2005-03-01

申请号：US09664516

申请日：2000-09-18

Applicant: James M. Dodd ,  Michael W. Williams

Inventor： James M. Dodd ,  Michael W. Williams

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1673

Abstract: A system and method for controlling the direction of data flow in a memory system is provided. The system comprising memory devices, a memory controller, a buffering structure, and a data flow director. The memory controller sends data, such as read-data, write-data, address information and command information, to the memory devices and receives data from the memory devices. The buffering structure interconnects the memory device and the memory controller. The buffering structure is adapted to operate in a bi-directional manner for the direction of data flow therethrough. The data flow director, which may reside in the buffering structure, the memory controller, the memory devices, or an external device, controls the direction of data flow through the buffering structure based on the data transmitted from the memory controller or the memory device.

Abstract translation: 提供了一种用于控制存储器系统中的数据流的方向的系统和方法。 该系统包括存储器件，存储器控制器，缓冲结构和数据流导向器。 存储器控制器将诸如读取数据，写入数据，地址信息和命令信息的数据发送到存储器件并从存储器件接收数据。 缓冲结构将存储器件和存储器控制器互连。 缓冲结构适于以双向方式操作数据流动的方向。 可以驻留在缓冲结构中的数据流导向器，存储器控制器，存储器件或外部设备基于从存储器控制器或存储器件发送的数据来控制通过缓冲结构的数据流的方向。

公开(公告)号：US06801459B2

公开(公告)日：2004-10-05

申请号：US10104837

申请日：2002-03-22

Applicant: Robert J. Riesenman ,  James M. Dodd ,  Michael W. WIlliams

Inventor： Robert J. Riesenman ,  James M. Dodd ,  Michael W. WIlliams

IPC: G11C1604

CPC classification number: G06F13/1626 ,  G06F12/04

Abstract: A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.

Abstract translation: 数据掩模图可以以各种方式编程到存储设备中。 在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。 在另一个实施例中，从存储器中的位置检索数据掩码图。 在另一个实施例中，通过算法确定数据掩码图。

公开(公告)号：US06772352B1

公开(公告)日：2004-08-03

申请号：US09677137

申请日：2000-09-29

Applicant: Michael W. Williams ,  James M. Dodd

Inventor： Michael W. Williams ,  James M. Dodd

IPC: G06F1200

CPC classification number: G11C11/406

Abstract: A method of issuing activate commands to a memory device includes issuing the activate commands to the memory device. A number of activate commands issued within a time period is counted. A determination is made as to whether the number of activate commands issued within the time period exceeds a threshold. The rate at which the activate commands are being issued is lowered if the number of activate commands being issued exceeds the threshold within the time period.

Abstract translation: 向存储器件发出激活命令的方法包括向存储器件发出激活命令。 对一段时间内发出的激活命令进行计数。 确定在该时间段内发出的激活命令的数量是否超过阈值。 如果发出的激活命令的数量在该时间段内超过阈值，则降低激活命令的发出速率。

公开(公告)号：US06553449B1

公开(公告)日：2003-04-22

申请号：US09675348

申请日：2000-09-29

Applicant: James M. Dodd ,  Michael W. Williams

Inventor： James M. Dodd ,  Michael W. Williams

IPC: G06F1200

CPC classification number: G06F13/1684 ,  Y02D10/14

Abstract: A system and method for providing concurrent column and row operations in a memory system is provided. The memory system includes a memory controller, a plurality of memory devices, and communication paths between the memory controller and the plurality of memory devices. The memory controller is coupled to each memory device through a communication path that provides a column chip select signal to the memory device and a communication path that provides a row chip select signal to the memory device. The dual chip select signals allow a column operation to be carried out in the memory device simultaneously with a row operation in the memory device. The communication paths further include a column command communication path that provides column commands to the memory devices, a column address communication path that provides column addresses for the column commands to the memory devices, a row command communication path that provides row commands to the memory devices, and a row address communication path that provides row addresses for the row commands to the memory device.

Abstract translation: 提供了一种用于在存储器系统中提供并行列和行操作的系统和方法。 存储器系统包括存储器控制器，多个存储器件以及存储器控制器和多个存储器件之间的通信路径。 存储器控制器通过将存储器件提供列选择信号的通信路径和向存储器件提供行片选信号的通信路径耦合到每个存储器件。 双芯片选择信号允许在存储设备中与行操作同时执行列操作。 通信路径还包括向存储器件提供列命令的列命令通信路径，向存储器件提供列命令的列地址的列地址通信路径，向存储器件提供行命令的行命令通信路径 以及行地址通信路径，其向行存储器设备提供行命令的行地址。