公开(公告)号：US5539465A

公开(公告)日：1996-07-23

申请号：US478937

申请日：1995-06-07

申请人： Frank Xu ,  Robert M. Nally

发明人： Frank Xu ,  Robert M. Nally

IPC分类号： H04N5/92 ,  H04N7/08

CPC分类号： H04N7/0806 ,  H04N5/9205

摘要： A method is provided for generating a plurality of displays from a composite video data stream comprising a plurality of frames each including two portions, a first portion of each frame containing data defining even fields of respective first and second displays and a second one of the portions of each frame containing data defining odd fields of the first and second displays. During first and second phases of a set of processing phases, data defining the odd and even fields of the first display are extracted from each received frame. Also during the first and third phases, the extracted data defining the odd and even fields of the first display are written into a first object buffer. During second and fourth phases of the set of processing phases, data defining the odd and even fields of the second display are extracted from each received frame. Also during the second and fourth phases, the extracted data defining the odd and even fields of the second display is written into a second object buffer. During the third and fourth phases, the first display data stored in the first object buffer is retrieved to drive a display device for generating the first display. During the second and fourth phases, the second display data stored in the second object buffer is retrieved to drive a display device for generating the second display.

摘要翻译： 提供一种用于从包括多个帧的复合视频数据流生成多个显示器的方法，每个帧包括两个部分，每个帧的第一部分包含定义相应的第一和第二显示器的偶数场的数据，以及第二部分 每个帧包含定义第一和第二显示器的奇数场的数据。 在一组处理阶段的第一和第二阶段期间，从每个接收的帧中提取定义第一显示的奇数和偶数场的数据。 此外，在第一和第三阶段期间，定义第一显示的奇数和偶数场的提取数据被写入第一对象缓冲器。 在一组处理阶段的第二和第四阶段，从每个接收的帧中提取定义第二显示的奇数和偶数场的数据。 同样在第二和第四阶段期间，定义第二显示器的奇数和偶数场的提取数据被写入第二对象缓冲器。 在第三和第四阶段期间，检索存储在第一对象缓冲器中的第一显示数据，以驱动用于产生第一显示的显示装置。 在第二和第四阶段期间，检索存储在第二对象缓冲器中的第二显示数据，以驱动用于产生第二显示的显示装置。

公开(公告)号：US5251298A

公开(公告)日：1993-10-05

申请号：US661076

申请日：1991-02-25

申请人： Robert M. Nally

发明人： Robert M. Nally

IPC分类号： G06F9/38 ,  G06T17/00 ,  G09G5/02 ,  G06F15/00

CPC分类号： G06F9/3877 ,  G06T17/00 ,  G09G5/02

摘要： A pixel color processor that performs supplemental graphical processing duties in a video unit in a computer system. The pixel color processor is interfaced between a processor and video memory and performs pixel string manipulation and color management duties on the pixel color data at the direction of the processor, thereby freeing up the processor of these duties. The memory address space of the processor includes a monochrome memory area which maps onto the full-depth packed-pixel video memory. When the processor performs operations on this monochrome area, the pixel color processor intercepts the addresses data generated by the processor and performs the pixel block transfers.

摘要翻译： 一种在计算机系统中的视频单元中执行补充图形处理任务的像素彩色处理器。 像素颜色处理器在处理器和视频存储器之间进行接口，并且在处理器的方向对像素颜色数据执行像素串操作和色彩管理任务，从而释放处理器的这些任务。 处理器的存储器地址空间包括映射到全深度压缩像素视频存储器的单色存储器区域。 当处理器对该单色区域执行操作时，像素彩色处理器截取由处理器生成的地址数据，并执行像素块传送。

公开(公告)号：US5910919A

公开(公告)日：1999-06-08

申请号：US903390

申请日：1997-07-30

申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

CPC分类号： G11C7/00 ,  G11C7/1006

摘要： A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

摘要翻译： 存储器系统104包括排列成行和列的存储器调用的阵列200和用于使用接收到的修改数据的位选择性地对存储在所选择的呼叫中的数据的位进行逻辑运算的逻辑运算，以及用于选择逻辑的模式数据位 操作性能。 当修改数据的位是逻辑1并且当修改数据的位为逻辑0时，保持存储在调用中的现有位，在修改数据的位的写入位期间将修改数据写入单元中的电路208。 存储器系统104还包括用于通过单个端口接收和锁存模式数据和修改数据的电路207,210。

公开(公告)号：US5625379A

公开(公告)日：1997-04-29

申请号：US402935

申请日：1995-03-13

申请人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

发明人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/36 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G5/40 ,  H04N9/64 ,  G09G5/04

CPC分类号： H04N9/641 ,  G09G5/006 ,  G09G5/008 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/40 ,  G09G2310/0232 ,  G09G2320/0606 ,  G09G2320/0673 ,  G09G2340/0407 ,  G09G2340/125

摘要： A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

摘要翻译： 提供显示接口装置20，其包括用于接收视频数据字的输入，视频数据字包括用于控制显示器的输出格式的控制代码和从相关视频控制器接收的视频时钟信号。 先进先出存储器30还具有通过第一时钟定时存入存储器30的视频数据字，并通过从相关图形控制器接收的时钟产生的第二时钟从存储器30中输出。

公开(公告)号：US5598525A

公开(公告)日：1997-01-28

申请号：US376919

申请日：1995-01-23

申请人： Robert M. Nally ,  John C. Schafer

发明人： Robert M. Nally ,  John C. Schafer

IPC分类号： G06T11/20 ,  G06F15/00

CPC分类号： G06T11/203

摘要： A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

摘要翻译： 提供了图形和视频控制器105，其包括用于接收图形和视频像素数据的单词的双孔径接口206，这些数据的每个单词与将要处理的字作为图形或视频数据相关联的地址相关联。 提供电路200,201,202,207,208，用于将从接口206接收的像素数据的字写入对应于与接收到的字相关联的地址的开和关屏幕之间的存储区域中的一个。 提供电路201,202用于从屏幕上和离屏存储区域选择性地检索图形和视频数据。 提供第一流水线205，用于处理从帧缓冲器107的屏幕上区域接收的数据，同时提供第二流水线204用于处理从帧缓冲器的屏幕外区域检索的数据。

公开(公告)号：US5577203A

公开(公告)日：1996-11-19

申请号：US402934

申请日：1995-03-13

申请人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

发明人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/36 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G5/40 ,  H04N9/64

CPC分类号： H04N9/641 ,  G09G5/006 ,  G09G5/008 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/40 ,  G09G2310/0232 ,  G09G2320/0606 ,  G09G2320/0673 ,  G09G2340/0407 ,  G09G2340/125

摘要： Methods are provided for transferring a stream of video data from a video data source to a display interface unit 20. A video data word is clocked into a first-in-first-out memory 30 by a first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

摘要翻译： 提供了用于将视频数据流从视频数据源传输到显示接口单元20的方法。视频数据字通过第一时钟被定时输入先进先出存储器30，并通过 从从相关联的图形控制器接收的时钟产生的第二时钟。

公开(公告)号：US5455626A

公开(公告)日：1995-10-03

申请号：US152182

申请日：1993-11-15

申请人： Frank Xu ,  Robert M. Nally

发明人： Frank Xu ,  Robert M. Nally

IPC分类号： H04N5/92 ,  H04N7/08

CPC分类号： H04N7/0806 ,  H04N5/9205

摘要： A method is provided for generating a output composite video data stream. During a first phase of a set of processing phases, a frame of first video data is received and then downscaled to produce a first block of data. Also during the first phase, the first block is stored and then retrieved from a first memory space. The first block is next upscaled and then output as a first field of a composite video data stream. During a second phase of the set of processing phases, a frame of second video data is received and downscaled to produce a second block of data. Also during the second phase, the second block of data is stored and then retrieved from a second memory space. The second block is next upscaled during the second processing phase and then output as a second field of the composite video stream.

摘要翻译： 提供了一种用于产生输出复合视频数据流的方法。 在一组处理阶段的第一阶段期间，接收第一视频数据的帧，然后将其缩小以产生第一数据块。 同样在第一阶段期间，第一块被存储，然后从第一存储空间检索。 第一个块被放大，然后作为复合视频数据流的第一个字段输出。 在该组处理阶段的第二阶段期间，接收并缩小第二视频数据的帧以产生第二数据块。 同样在第二阶段期间，存储第二数据块，然后从第二存储器空间检索。 第二块在第二处理阶段接着放大，然后作为复合视频流的第二个字段输出。

公开(公告)号：US5440683A

公开(公告)日：1995-08-08

申请号：US328382

申请日：1994-10-20

申请人： Robert M. Nally ,  John C. Schafer

发明人： Robert M. Nally ,  John C. Schafer

IPC分类号： G11B27/02 ,  G11B27/031 ,  G11B27/032 ,  H04N5/262 ,  H04N5/91 ,  H04N5/92 ,  H04N9/79 ,  G06F15/00

CPC分类号： H04N5/262 ,  G11B27/031

摘要： A digital video editor employing a single chip special-purpose digital video processing unit (VPU) having the capability to combine several different digital video input signals into a single digital video output signal is disclosed. The VPU comprises a microprocessor operating under a set of instructions which is operative for receiving, storing and manipulating portions of an incoming digital video signal and a delay circuit, coupled to the microprocessor, for delaying execution of a particular instruction if a particular portion upon which the instruction is to operate has not yet been stored. The VPU processes multiple digitized video signals in real time in a time-sharing fashion because its processing speed is substantially greater than the rate at which it receives video data and processes multiple picture elements of a single digital stream simultaneously. In a preferred environment, The VPU operates in conjunction with an IBM compatible personal computer, an inexpensive general purpose computer. By processing video digitally, the VPU avoids generation loss and allows efficient digital compression and storage of video data.

摘要翻译： 公开了一种采用单芯片专用数字视频处理单元（VPU）的数字视频编辑器，其具有将多个不同的数字视频输入信号组合成单个数字视频输出信号的能力。 VPU包括在一组指令下操作的微处理器，其操作用于接收，存储和操纵耦合到微处理器的输入数字视频信号和延迟电路的部分，用于延迟特定指令的执行，如果其上的特定部分 指令操作尚未存储。 VPU以时分方式实时处理多个数字化视频信号，因为它的处理速度明显大于其接收视频数据的速率并且同时处理单个数字流的多个图像元素。 在优选的环境中，VPU与IBM兼容的个人计算机（便宜的通用计算机）一起运行。 通过数字处理视频，VPU避免了生成丢失，并允许视频数据的高效数字压缩和存储。

公开(公告)号：US06825845B2

公开(公告)日：2004-11-30

申请号：US10109030

申请日：2002-03-28

申请人： Robert M. Nally

发明人： Robert M. Nally

IPC分类号： G09G536

CPC分类号： G09G5/393 ,  G09G5/14

摘要： A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

摘要翻译： 一种用于在一个LCD面板上级联多个显示控制器的虚拟帧缓冲器控制系统和方法。 虚拟帧缓冲器由所有控制器/存储器/源驱动器芯片（以平铺图案形式）的所有存储器组成，用于相关处理器的读写。控制系统还包括每个控制器/ 内存/源驱动程序芯片。 虚拟帧缓冲器和硬件限幅控制放置大大减少了与用于级联LCD控制器/存储器/源驱动器设备的现有技术解决方案相关联的编程问题。

公开(公告)号：US5914900A

公开(公告)日：1999-06-22

申请号：US902674

申请日：1997-07-30

申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C7/00 ,  G11C7/1006

摘要： A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.

摘要翻译： 存储器系统104包括以行和列布置的存储器单元的阵列200。 包括电路208，用于使用接收到的修改数据的位和用于选择用于性能的逻辑运算的模式数据位来选择性地对存储在所选择的单元中的一组数据执行逻辑运算。 用于执行逻辑运算的电路208在AND逻辑运算期间可操作以在修改数据的位为逻辑零时将数据写入单元，并且当修改数据的位为逻辑1时，保持存储在单元中的现有位。 还包括用于通过单个端口接收和锁存模式数据位和修改数据的电路207,210。