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1.发明授权Circuits, systems and methods for modifying data stored in a memory using logic operations 失效使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法
公开(公告)号：US5910919A
公开(公告)日：1999-06-08
申请号：US903390
申请日：1997-07-30
申请人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
发明人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
CPC分类号： G11C7/00 , G11C7/1006
摘要： A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.
摘要翻译： 存储器系统104包括排列成行和列的存储器调用的阵列200和用于使用接收到的修改数据的位选择性地对存储在所选择的呼叫中的数据的位进行逻辑运算的逻辑运算，以及用于选择逻辑的模式数据位 操作性能。 当修改数据的位是逻辑1并且当修改数据的位为逻辑0时，保持存储在调用中的现有位，在修改数据的位的写入位期间将修改数据写入单元中的电路208。 存储器系统104还包括用于通过单个端口接收和锁存模式数据和修改数据的电路207,210。
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2.发明授权Circuits, systems and methods for modifying data stored in a memory using logic operations 失效使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法
公开(公告)号：US5914900A
公开(公告)日：1999-06-22
申请号：US902674
申请日：1997-07-30
申请人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
发明人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
CPC分类号： G11C7/00 , G11C7/1006
摘要： A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.
摘要翻译： 存储器系统104包括以行和列布置的存储器单元的阵列200。 包括电路208，用于使用接收到的修改数据的位和用于选择用于性能的逻辑运算的模式数据位来选择性地对存储在所选择的单元中的一组数据执行逻辑运算。 用于执行逻辑运算的电路208在AND逻辑运算期间可操作以在修改数据的位为逻辑零时将数据写入单元，并且当修改数据的位为逻辑1时，保持存储在单元中的现有位。 还包括用于通过单个端口接收和锁存模式数据位和修改数据的电路207,210。
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公开(公告)号：US5909401A
公开(公告)日：1999-06-01
申请号：US903317
申请日：1997-07-30
申请人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
发明人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
CPC分类号： G11C7/00 , G11C7/1006
摘要： Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.
摘要翻译： 感测电路包括读出放大器400，用于在真位位线上锁存数据位，并在互补位线上锁存数据的互补位。 包括电路403,404,405，用于响应于修改数据的位，对读出放大器400中锁存的数据的位进行布尔运算。 在AND操作期间的电路403,404,405在将数据修改为逻辑0的位时，拉低真位位线。
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4.发明授权Circuits, systems and methods for modifying data stored in a memory using logic operations 失效使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法
公开(公告)号：US5732024A
公开(公告)日：1998-03-24
申请号：US424653
申请日：1995-04-19
申请人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
发明人： Sudhir Sharma , Michael E. Runas , Robert M. Nally
CPC分类号： G11C7/00 , G11C7/1006
摘要： A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.
摘要翻译： 提供了一种存储器系统104，其包括以行和列布置的存储器单元的阵列200。 还提供电路207,208,209,210，用于使用接收到的修改数据的位来选择性地对存储在所选择的存储器单元中的数据的位进行逻辑运算。 用于执行逻辑操作的电路207,208,209,210在AND操作期间可操作以在修改数据的位为逻辑0时将修改数据的位写入所选存储单元，并维持存储在所选单元中的现有位 当修改数据的位是逻辑位时。
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5.发明授权Display controller with integrated half frame buffer and systems and methods using the same 失效具有集成半帧缓冲器的显示控制器及使用其的系统和方法
公开(公告)号：US5945974A
公开(公告)日：1999-08-31
申请号：US645021
申请日：1996-05-15
申请人： Sudhir Sharma , G.R. Mohan Rao , Michael E. Runas
发明人： Sudhir Sharma , G.R. Mohan Rao , Michael E. Runas
CPC分类号： G09G3/3644 , G09G3/3611 , G09G5/363
摘要： A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.
摘要翻译： 一种与显示装置107一起使用的显示控制器104，其可操作以在屏幕上显示图像。 显示控制器104包括用于向显示设备107呈现第一数据以用于在屏幕的第一区域中生成图像的电路201-210，第一数据从外部帧缓冲器108检索。显示控制器104还包括电路205， 210，用于向显示装置107呈现第二数据，用于在屏幕的第二区域中生成图像，第二数据从内部帧缓冲器206检索。
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6.发明授权Memory system with multiplexed input-output port and memory mapping capability 失效具有复用输入输出端口和内存映射功能的内存系统
公开(公告)号：US5835965A
公开(公告)日：1998-11-10
申请号：US637073
申请日：1996-04-24
IPC分类号： G11C11/401 , G06F12/02 , G06F12/06 , G11C5/06 , G06F12/00
CPC分类号： G11C5/066 , G06F12/0292
摘要： A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.
摘要翻译： 存储器600，其包括存储器单元201的阵列和用于在控制周期期间接收控制位的多个输入/输出端子220，并且在数据访问周期期间访问单元201中的选定单元201。 提供命令位输入端221用于接收用于启动控制周期的命令位，并且提供映射输入端222用于接收映射使能信号以启动映射模式。 提供电路215/216用于解码在映射模式期间发生的至少一个控制周期期间接收到的控制位，用于允许映射用于访问阵列201的单元的一组地址。
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7.发明授权Memory system with multiplexed input-output port and systems and methods using the same 失效具有复用输入输出端口的内存系统及使用其的系统和方法
公开(公告)号：US5829016A
公开(公告)日：1998-10-27
申请号：US638953
申请日：1996-04-24
CPC分类号： G06F13/1678
摘要： A memory including a plurality of input/output terminals 220 for exchanging data bits during a data access cycle and receiving command and control bits during a command and control cycle. The memory further includes an array of memory cells 201, a data input/output circuitry for transferring data between the input/output terminals and the array of memory cells during the data access cycle, and control circuitry for controlling operations of the memory in response to command and control bits received at the input/output terminals during the command and control cycle.
摘要翻译： 一种存储器，包括用于在数据访问周期期间交换数据位的多个输入/输出端子220，以及在命令和控制周期期间接收命令和控制位。 存储器还包括存储单元阵列201，用于在数据访问周期期间在输入/输出端子与存储器单元阵列之间传送数据的数据输入/输出电路，以及响应于存储器单元201控制存储器的操作的控制电路 在命令和控制周期中，在输入/输出端接收的命令和控制位。
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公开(公告)号：US08559249B1
公开(公告)日：2013-10-15
申请号：US13431424
申请日：2012-03-27
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
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9.发明授权Dual bank memory system with output multiplexing and methods using the same 失效具有输出多路复用的双行存储器系统及其使用方法
公开(公告)号：US5570320A
公开(公告)日：1996-10-29
申请号：US554297
申请日：1995-11-06
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/04 , G11C8/00
CPC分类号： G11C7/1021 , G11C7/00
摘要： A memory circuit 300 is provided which includes first and second banks 201a and 201b of memory cells arranged in rows and columns. Row decoder circuitry 210 is provided for selecting a row in at least one of the banks in response to row address. Row address circuitry 208, 209 is included for providing a sequence of row addresses to the row decoder circuitry in response to a single row address received at an address port to memory circuitry 300. Column decoder circuitry 213 is provided for selecting columns in each of the banks 201 in response to a column address. Column address circuitry 211, 212 is provided for presenting a sequence of column addresses to the column decoder circuitry in response to a single column address received at the address port.
摘要翻译： 提供存储电路300，其包括以行和列排列的存储单元的第一和第二存储体201a和201b。 行解码器电路210被提供用于响应于行地址来选择至少一个存储体中的行。 包括行地址电路208,209，用于响应于在存储器电路300的地址端口处接收到的单行地址，向行解码器电路提供行地址序列。列解码器电路213被提供用于在每个 银行201响应列地址。 列地址电路211,212被提供用于响应于在地址端口处接收到的单列地址，向列解码器电路呈现列地址序列。
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公开(公告)号：US5455526A
公开(公告)日：1995-10-03
申请号：US288442
申请日：1994-08-10
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/0175 , H03K19/094
CPC分类号： H03K3/356017 , H03K3/356113
摘要： A digital voltage shifter 101 is provided which includes an input buffer 200 having an input for receiving data logic high signals at a first voltage, a true output and a complementary output. A static random access memory cell 220 is also included which operates in response to a voltage supply providing a second voltage differing from the first voltage and having a first input coupled to the true output of the input buffer and a second input coupled to the complementary output of the input buffer. An output driver 230 is further included which operates in response to the second supply voltage and is coupled to an output of the memory cell, the output driver outputting the received logic signals at the second voltage.
摘要翻译： 提供数字电压转换器101，其包括具有用于在第一电压，真实输出和互补输出处接收数据逻辑高信号的输入的输入缓冲器200。 还包括静态随机存取存储器单元220，其响应于提供不同于第一电压的第二电压的电压供应并且具有耦合到输入缓冲器的真实输出的第一输入和耦合到互补输出的第二输入 的输入缓冲区。 还包括输出驱动器230，其响应于第二电源电压而操作并耦合到存储器单元的输出，输出驱动器以第二电压输出接收的逻辑信号。
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