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19 条记录 (耗时 0.018 秒)

    Memory system with multiplexed input-output port and memory mapping capability
    1.
    发明授权
    Memory system with multiplexed input-output port and memory mapping capability 失效
    具有复用输入输出端口和内存映射功能的内存系统

    公开(公告)号：US5835965A

    公开(公告)日：1998-11-10

    申请号：US637073

    申请日：1996-04-24

    申请人： Ronald T. Taylor ,  Sudhir Sharma ,  Michael E. Runas

    发明人： Ronald T. Taylor ,  Sudhir Sharma ,  Michael E. Runas

    IPC分类号： G11C11/401 ,  G06F12/02 ,  G06F12/06 ,  G11C5/06 ,  G06F12/00

    CPC分类号： G11C5/066 ,  G06F12/0292

    摘要： A memory 600 including an array of memory cells 201 and a plurality of input/output terminals 220 for receiving control bits during control cycles and accessing selected ones of the cells 201 during data access cycles. A command bit input terminal 221 is provided for receiving command bits for initiating the control cycles and a mapping input terminal 222 is provided for receiving a mapping enable signal to initiate a mapping mode. Circuitry 215/ 216 is provided for decoding control bits received during at least one control cycle occurring during a mapping mode for allowing a mapping of a set of addresses for accessing the cells of the array 201.

    摘要翻译： 存储器600，其包括存储器单元201的阵列和用于在控制周期期间接收控制位的多个输入/输出端子220，并且在数据访问周期期间访问单元201中的选定单元201。 提供命令位输入端221用于接收用于启动控制周期的命令位，并且提供映射输入端222用于接收映射使能信号以启动映射模式。 提供电路215/216用于解码在映射模式期间发生的至少一个控制周期期间接收到的控制位，用于允许映射用于访问阵列201的单元的一组地址。

    Circuits, systems and methods for testing integrated circuit devices including logic and memory circuitry
    2.
    发明授权
    Circuits, systems and methods for testing integrated circuit devices including logic and memory circuitry 失效
    用于测试集成电路器件（包括逻辑和存储器电路）的电路，系统和方法

    公开(公告)号：US5535165A

    公开(公告)日：1996-07-09

    申请号：US497267

    申请日：1995-06-30

    申请人： Phillip D. Davis ,  Sudhir Sharma ,  Hai Long

    发明人： Phillip D. Davis ,  Sudhir Sharma ,  Hai Long

    IPC分类号： G06F11/273 ,  G11C29/48 ,  G11C7/00 ,  G01R31/28 ,  G11C29/00

    CPC分类号： G11C29/48 ,  G06F11/2733

    摘要： A single chip integrated circuit 200 is disclosed which includes logic circuitry 202, memory circuitry 204, and a bus 300. First bus control circuitry 302 controls the exchange of signals between logic circuitry 202 and bus 300. Second bus control circuitry 303 controls the exchange of signals between memory circuitry 204 and bus 300. Third bus control circuitry 306 is included which controls the exchange of signals between bus 300 and at least one test pin 206. Mode control circuitry 205 is operable as control circuitry 302, 303, and 306. In the operating mode, mode control circuitry 205 activates first bus control circuitry 302 and second bus control circuitry 303. In a memory test mode, mode control circuitry 205 activates second bus control circuitry 303 and third bus control circuitry 306 and deactivates first bus control circuitry 302. In a logic test mode, test mode circuitry 205 activates first bus control circuitry 302 and third bus control circuitry 306 and deactivates second bus control circuitry 303.

    摘要翻译： 公开了一种单芯片集成电路200，其包括逻辑电路202，存储器电路204和总线300.第一总线控制电路302控制逻辑电路202与总线300之间的信号交换。第二总线控制电路303控制 存储器电路204和总线300之间的信号。包括第三总线控制电路306，其控制总线300与至少一个测试引脚206之间的信号交换。模式控制电路205可操作为控制电路302,303和306。 操作模式模式控制电路205激活第一总线控制电路302和第二总线控制电路303.在存储器测试模式中，模式控制电路205激活第二总线控制电路303和第三总线控制电路306，并使第一总线控制电路302 在逻辑测试模式中，测试模式电路205激活第一总线控制电路302和第三总线控制电路306并且使第二总线控制电路306停用 总线控制电路303。

    METHOD AND SYSTEM FOR SOCIAL COMMERCE AND GROUP DEAL PURCHASING
    3.
    发明申请
    METHOD AND SYSTEM FOR SOCIAL COMMERCE AND GROUP DEAL PURCHASING 有权

    公开(公告)号：US20230035712A1

    公开(公告)日：2023-02-02

    申请号：US17876411

    申请日：2022-07-28

    申请人： Inna Vedavyasa Sudhir Sharma ,  Chandra Shekar Gowda ,  Vishal Nangani

    发明人： Inna Vedavyasa Sudhir Sharma ,  Chandra Shekar Gowda ,  Vishal Nangani

    IPC分类号： G06Q30/06

    摘要： A computer-implemented method comprising, receiving, by one or more processors, a request to create a listing for a purchase of a product or service, wherein a quantity of greater than two of the product or service is required, analyzing, by one or more processors, a set of requirements to purchase the product or service based on a set of seller's requirements, applying, by one or more processors, the set of seller requirements to the listing, wherein the listing is depicted within a user interface, determining, by one or more processors, if a length of time restrictions has expired or a predetermined number of purchasers have joined the listing to purchase the product or service, wherein a user interface is manipulated based on the determination, and processing, by one or more processors, the listing based on the determination.

    Systems and methods for passively transferring data across a selected single bus line independent of a control circuitry
    4.
    发明授权
    Systems and methods for passively transferring data across a selected single bus line independent of a control circuitry 失效
    用于被动地传输数据的系统和方法，所述数据跨选择的单个总线独立于控制电路

    公开(公告)号：US06425020B1

    公开(公告)日：2002-07-23

    申请号：US08843569

    申请日：1997-04-18

    申请人： Sudhir Sharma

    发明人： Sudhir Sharma

    IPC分类号： G06F1314

    CPC分类号： G06F13/423

    摘要： Processing circuiter 100 is provided having a passive data transfer capability. Processing circuitry 100 includes a bus 116, a first subsystem 105 coupled to bus 116 through first passive transfer logic 120a, and a second subsystem 108 coupled to bus 116 through second passive transfer logic 120b. Processing circuitry 100 further includes control circuitry 101/103 coupled to bus 116 for initiating a passive data transfer between first and second subsystems 105 and 108, first and second passive transfer logic 120a and 120b there after controlling exchange of data between the first and second subsystems 105 and 108 independent of the control circuitry 101/103.

    摘要翻译： 提供处理电路100具有无源数据传输能力。 处理电路100包括总线116，通过第一无源传输逻辑120a耦合到总线116的第一子系统105以及通过第二无源传输逻辑120b耦合到总线116的第二子系统108。 处理电路100还包括耦合到总线116的控制电路101/103，用于在控制第一和第二子系统之间的数据交换之后启动第一和第二子系统105和108之间的无源数据传输，第一和第二无源传输逻辑120a和120b 105和108独立于控制电路101/103。

    Circuits, systems and methods for graphics and video window/display data block transfer via dedicated memory control
    5.
    发明授权
    Circuits, systems and methods for graphics and video window/display data block transfer via dedicated memory control 失效
    图形和视频窗口的电路，系统和方法/通过专用存储器控制显示数据块传输

    公开(公告)号：US6157366A

    公开(公告)日：2000-12-05

    申请号：US862325

    申请日：1997-05-23

    申请人： Sudhir Sharma

    发明人： Sudhir Sharma

    IPC分类号： G09G5/14 ,  G09G5/39 ,  G09G5/395 ,  G09G5/397

    CPC分类号： G09G5/14 ,  G09G5/397

    摘要： Display control circuitry is provided which includes a frame buffer 104 having a plurality of memory spaces 301 each for storing a block of display data. Circuitry 200 is provided for generating display position data representing a position on a display screen corresponding to a current display pixel being generated. For each memory space 301, a window control circuit 201 is provided for controlling the transfer of a block of data from the given memory space 301 to a selected window on the display screen. Each window control circuit 201 includes first registers 205, 206 for storing data defining horizontal boundaries of the window, second registers 210, 211 for storing data defining vertical boundaries of the window, and circuitry 207, 208, 209, 212, 213, 214 for comparing the display position data with data stored in the first and second registers and generate an enable signal when the position on the screen of the current pixel is within the window boundaries. Memory control circuitry 300, 302 is provided for retrieving data from the memory space 301 selected in response to the enable signals received from the window control circuits 201.

    摘要翻译： 提供了显示控制电路，其包括具有多个存储空间301的帧缓冲器104，每个存储器空间301用于存储显示数据块。 提供电路200，用于产生表示与正在生成的当前显示像素对应的显示屏上的位置的显示位置数据。 对于每个存储器空间301，提供了一个窗口控制电路201，用于控制从给定存储器空间301到显示屏上的选定窗口的数据块的传送。 每个窗口控制电路201包括用于存储定义窗口水平边界的数据的第一寄存器205,206，用于存储定义该窗口的垂直边界的数据的第二寄存器210,211以及电路207,208,209,212,213,214，用于 将显示位置数据与存储在第一和第二寄存器中的数据进行比较，并且当当前像素的屏幕上的位置在窗口边界内时产生使能信号。 存储器控制电路300,302用于从响应于从窗口控制电路201接收到的使能信号而选择的存储器空间301检索数据。

    Display controller with integrated half frame buffer and systems and methods using the same
    9.
    发明授权
    Display controller with integrated half frame buffer and systems and methods using the same 失效
    具有集成半帧缓冲器的显示控制器及使用其的系统和方法

    公开(公告)号：US5945974A

    公开(公告)日：1999-08-31

    申请号：US645021

    申请日：1996-05-15

    申请人： Sudhir Sharma ,  G.R. Mohan Rao ,  Michael E. Runas

    发明人： Sudhir Sharma ,  G.R. Mohan Rao ,  Michael E. Runas

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/36 ,  G09G5/39

    CPC分类号： G09G3/3644 ,  G09G3/3611 ,  G09G5/363

    摘要： A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.

    摘要翻译： 一种与显示装置107一起使用的显示控制器104，其可操作以在屏幕上显示图像。 显示控制器104包括用于向显示设备107呈现第一数据以用于在屏幕的第一区域中生成图像的电路201-210，第一数据从外部帧缓冲器108检索。显示控制器104还包括电路205， 210，用于向显示装置107呈现第二数据，用于在屏幕的第二区域中生成图像，第二数据从内部帧缓冲器206检索。

    Circuits, systems and methods for modifying data stored in a memory using logic operations
    10.
    发明授权
    Circuits, systems and methods for modifying data stored in a memory using logic operations 失效
    使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法

    公开(公告)号：US5910919A

    公开(公告)日：1999-06-08

    申请号：US903390

    申请日：1997-07-30

    申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

    摘要翻译： 存储器系统104包括排列成行和列的存储器调用的阵列200和用于使用接收到的修改数据的位选择性地对存储在所选择的呼叫中的数据的位进行逻辑运算的逻辑运算，以及用于选择逻辑的模式数据位 操作性能。 当修改数据的位是逻辑1并且当修改数据的位为逻辑0时，保持存储在调用中的现有位，在修改数据的位的写入位期间将修改数据写入单元中的电路208。 存储器系统104还包括用于通过单个端口接收和锁存模式数据和修改数据的电路207,210。