利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

21 条记录 (耗时 0.019 秒)

    Apparatus, systems and methods for providing multiple video data streams from a single source
    1.
    发明授权
    Apparatus, systems and methods for providing multiple video data streams from a single source 失效
    用于从单个源提供多个视频数据流的装置，系统和方法

    公开(公告)号：US5539465A

    公开(公告)日：1996-07-23

    申请号：US478937

    申请日：1995-06-07

    申请人： Frank Xu ,  Robert M. Nally

    发明人： Frank Xu ,  Robert M. Nally

    IPC分类号： H04N5/92 ,  H04N7/08

    CPC分类号： H04N7/0806 ,  H04N5/9205

    摘要： A method is provided for generating a plurality of displays from a composite video data stream comprising a plurality of frames each including two portions, a first portion of each frame containing data defining even fields of respective first and second displays and a second one of the portions of each frame containing data defining odd fields of the first and second displays. During first and second phases of a set of processing phases, data defining the odd and even fields of the first display are extracted from each received frame. Also during the first and third phases, the extracted data defining the odd and even fields of the first display are written into a first object buffer. During second and fourth phases of the set of processing phases, data defining the odd and even fields of the second display are extracted from each received frame. Also during the second and fourth phases, the extracted data defining the odd and even fields of the second display is written into a second object buffer. During the third and fourth phases, the first display data stored in the first object buffer is retrieved to drive a display device for generating the first display. During the second and fourth phases, the second display data stored in the second object buffer is retrieved to drive a display device for generating the second display.

    摘要翻译： 提供一种用于从包括多个帧的复合视频数据流生成多个显示器的方法，每个帧包括两个部分，每个帧的第一部分包含定义相应的第一和第二显示器的偶数场的数据，以及第二部分 每个帧包含定义第一和第二显示器的奇数场的数据。 在一组处理阶段的第一和第二阶段期间，从每个接收的帧中提取定义第一显示的奇数和偶数场的数据。 此外，在第一和第三阶段期间，定义第一显示的奇数和偶数场的提取数据被写入第一对象缓冲器。 在一组处理阶段的第二和第四阶段，从每个接收的帧中提取定义第二显示的奇数和偶数场的数据。 同样在第二和第四阶段期间，定义第二显示器的奇数和偶数场的提取数据被写入第二对象缓冲器。 在第三和第四阶段期间，检索存储在第一对象缓冲器中的第一显示数据，以驱动用于产生第一显示的显示装置。 在第二和第四阶段期间，检索存储在第二对象缓冲器中的第二显示数据，以驱动用于产生第二显示的显示装置。

    Method and apparatus for auxiliary pixel color management using monomap addresses which map to color pixel addresses
    2.
    发明授权
    Method and apparatus for auxiliary pixel color management using monomap addresses which map to color pixel addresses 失效
    用于辅助像素颜色管理的方法和装置，使用映射到彩色像素地址的单像地址

    公开(公告)号：US5251298A

    公开(公告)日：1993-10-05

    申请号：US661076

    申请日：1991-02-25

    申请人： Robert M. Nally

    发明人： Robert M. Nally

    IPC分类号： G06F9/38 ,  G06T17/00 ,  G09G5/02 ,  G06F15/00

    CPC分类号： G06F9/3877 ,  G06T17/00 ,  G09G5/02

    摘要： A pixel color processor that performs supplemental graphical processing duties in a video unit in a computer system. The pixel color processor is interfaced between a processor and video memory and performs pixel string manipulation and color management duties on the pixel color data at the direction of the processor, thereby freeing up the processor of these duties. The memory address space of the processor includes a monochrome memory area which maps onto the full-depth packed-pixel video memory. When the processor performs operations on this monochrome area, the pixel color processor intercepts the addresses data generated by the processor and performs the pixel block transfers.

    摘要翻译： 一种在计算机系统中的视频单元中执行补充图形处理任务的像素彩色处理器。 像素颜色处理器在处理器和视频存储器之间进行接口，并且在处理器的方向对像素颜色数据执行像素串操作和色彩管理任务，从而释放处理器的这些任务。 处理器的存储器地址空间包括映射到全深度压缩像素视频存储器的单色存储器区域。 当处理器对该单色区域执行操作时，像素彩色处理器截取由处理器生成的地址数据，并执行像素块传送。

    LPC transaction bridging across a PCI—express docking connection
    3.
    发明授权
    LPC transaction bridging across a PCI—express docking connection 有权
    LPC交易桥接跨PCI-express对接连接

    公开(公告)号：US07096308B2

    公开(公告)日：2006-08-22

    申请号：US10651521

    申请日：2003-08-29

    申请人： Kevin K. Main ,  Robert M. Nally

    发明人： Kevin K. Main ,  Robert M. Nally

    IPC分类号： G06F13/16

    CPC分类号： G06F13/4027 ,  G06F2213/0026

    摘要： A hybrid PCI_Express fabric system allows LPC bus commands and data to be sent across the PCI_Express fabric from a portable computer to its docking station. This permits the portable computer to be coupled to peripheral devices connected to the docking station without additional connectors on the portable computer and the docking station.

    摘要翻译： 混合PCI_Express结构系统允许LPC总线命令和数据通过PCI_Express结构从便携式计算机发送到其对接站。 这允许便携式计算机耦合到连接到对接站的外围设备，而无需在便携式计算机和对接站上的附加连接器。

    Apparatus, systems and methods for generating displays from dual source composite data streams
    4.
    发明授权
    Apparatus, systems and methods for generating displays from dual source composite data streams 失效
    用于从双源复合数据流生成显示器的装置，系统和方法

    公开(公告)号：US5539464A

    公开(公告)日：1996-07-23

    申请号：US475382

    申请日：1995-06-07

    申请人： Frank Xu ,  Robert M. Nally

    发明人： Frank Xu ,  Robert M. Nally

    IPC分类号： H04N5/92 ,  H04N7/08

    CPC分类号： H04N7/0806 ,  H04N5/9205

    摘要： A method is provided for displaying data received as a composite video data stream, each frame of the composite data stream being composed of a field of data defining a first video display and a subsequent field defining a second video display. The composite video data stream is received and during first and third phases of a set of processing phases, the fields of data defining the first video display are stored in a first object buffer in memory. During second and fourth phases of the set of processing phases, the fields of data defining the second display are stored in a second object buffer in memory. During the first and third phases, the fields of data stored in the first object buffer are retrieved to generate the first display and during the second and fourth phases, the fields of data stoned in the second object buffer are retrieved to generate the second display.

    摘要翻译： 提供了一种用于显示作为复合视频数据流接收的数据的方法，所述复合数据流的每个帧由定义第一视频显示的数据区域和定义第二视频显示的后续字段组成。 接收复合视频数据流，并且在一组处理阶段的第一和第三阶段期间，将定义第一视频显示的数据字段存储在存储器中的第一对象缓冲器中。 在一组处理阶段的第二和第四阶段期间，定义第二显示的数据字段被存储在存储器中的第二对象缓冲器中。 在第一和第三阶段期间，检索存储在第一对象缓冲器中的数据的字段以产生第一显示，并且在第二和第四阶段期间，检索在第二对象缓冲器中写入的数据的字段以产生第二显示。

    Virtual frame buffer control system
    5.
    发明授权
    Virtual frame buffer control system 有权
    虚拟帧缓冲控制系统

    公开(公告)号：US06825845B2

    公开(公告)日：2004-11-30

    申请号：US10109030

    申请日：2002-03-28

    申请人： Robert M. Nally

    发明人： Robert M. Nally

    IPC分类号： G09G536

    CPC分类号： G09G5/393 ,  G09G5/14

    摘要： A Virtual Frame Buffer control system and method for cascading several display controllers on one LCD panel. The Virtual Frame Buffer is composed of all the memory in all the controller/memory/source driver chips (in a tiled pattern) for the associated processor to read and write in. The control system also includes hardware clipping controls in each of the controller/memory/source driver chips. The Virtual Frame Buffer and hardware clipping control placement substantially reduces programming problems associated with prior art solutions for cascading LCD controller/memory/source driver devices.

    摘要翻译： 一种用于在一个LCD面板上级联多个显示控制器的虚拟帧缓冲器控制系统和方法。 虚拟帧缓冲器由所有控制器/存储器/源驱动器芯片（以平铺图案形式）的所有存储器组成，用于相关处理器的读写。控制系统还包括每个控制器/ 内存/源驱动程序芯片。 虚拟帧缓冲器和硬件限幅控制放置大大减少了与用于级联LCD控制器/存储器/源驱动器设备的现有技术解决方案相关联的编程问题。

    Circuits, systems and methods for modifying data stored in a memory using logic operations
    6.
    发明授权
    Circuits, systems and methods for modifying data stored in a memory using logic operations 失效
    使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法

    公开(公告)号：US5914900A

    公开(公告)日：1999-06-22

    申请号：US902674

    申请日：1997-07-30

    申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C16/04

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： A memory system 104 includes an array 200 of memory cells arranged in rows and columns. Circuitry 208 is included for selectively performing logic operations on a bit of data stored in a selected cell using a bit of received modifying data and mode data bit for selecting a logic operation for performance. Circuitry 208 for performing logic operations is operable during an AND logic operation to write data into the cell when the bit of modifying data is a logic zero and maintaining an existing bit stored in the cell when the bit of modifying data is a logic one. Also included is circuitry 207, 210 for receiving and latching the mode data bit and the modifying data through a single port.

    摘要翻译： 存储器系统104包括以行和列布置的存储器单元的阵列200。 包括电路208，用于使用接收到的修改数据的位和用于选择用于性能的逻辑运算的模式数据位来选择性地对存储在所选择的单元中的一组数据执行逻辑运算。 用于执行逻辑运算的电路208在AND逻辑运算期间可操作以在修改数据的位为逻辑零时将数据写入单元，并且当修改数据的位为逻辑1时，保持存储在单元中的现有位。 还包括用于通过单个端口接收和锁存模式数据位和修改数据的电路207,210。

    Sensing circuitry with boolean logic
    7.
    发明授权
    Sensing circuitry with boolean logic 失效
    具有布尔逻辑的感应电路

    公开(公告)号：US5909401A

    公开(公告)日：1999-06-01

    申请号：US903317

    申请日：1997-07-30

    申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C16/04

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： Sensing circuitry including a sense amplifier 400 for latching a bit of data on a true bit line and a complementary bit of data on a complementary bit line. Circuitry 403, 404, 405 is included for performing boolean operations on bit of data latched in sense amplifier 400 in response to a bit of modifying data. Circuitry 403, 404, 405 during an AND operation pulls down the true bit line when the bit of modifying data a logic 0.

    摘要翻译： 感测电路包括读出放大器400，用于在真位位线上锁存数据位，并在互补位线上锁存数据的互补位。 包括电路403,404,405，用于响应于修改数据的位，对读出放大器400中锁存的数据的位进行布尔运算。 在AND操作期间的电路403,404,405在将数据修改为逻辑0的位时，拉低真位位线。

    Circuits, systems and methods for modifying data stored in a memory using logic operations
    8.
    发明授权
    Circuits, systems and methods for modifying data stored in a memory using logic operations 失效
    使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法

    公开(公告)号：US5732024A

    公开(公告)日：1998-03-24

    申请号：US424653

    申请日：1995-04-19

    申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： A memory system 104 is provided which includes an array 200 of memory cells arranged in rows and columns. Circuitry 207, 208, 209, 210 is also provided for selectively performing logic operations on a bit of data stored in a selected memory cell using a bit of received modifying data. Circuitry 207, 208, 209, 210 for performing logic operations is operable during an AND operation to write the bit of modifying data into the selected memory cell when the bit of modifying data is a logic zero and maintains an existing bit stored in the selected cell when the bit of modifying data is a logic one.

    摘要翻译： 提供了一种存储器系统104，其包括以行和列布置的存储器单元的阵列200。 还提供电路207,208,209,210，用于使用接收到的修改数据的位来选择性地对存储在所选择的存储器单元中的数据的位进行逻辑运算。 用于执行逻辑操作的电路207,208,209,210在AND操作期间可操作以在修改数据的位为逻辑0时将修改数据的位写入所选存储单元，并维持存储在所选单元中的现有位 当修改数据的位是逻辑位时。

    Circuits, systems and methods for modifying data stored in a memory using logic operations
    9.
    发明授权
    Circuits, systems and methods for modifying data stored in a memory using logic operations 失效
    使用逻辑运算来修改存储在存储器中的数据的电路，系统和方法

    公开(公告)号：US5910919A

    公开(公告)日：1999-06-08

    申请号：US903390

    申请日：1997-07-30

    申请人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    发明人： Sudhir Sharma ,  Michael E. Runas ,  Robert M. Nally

    IPC分类号： G11C11/401 ,  G06F12/00 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10 ,  G11C8/00

    CPC分类号： G11C7/00 ,  G11C7/1006

    摘要： A memory system 104 includes an array 200 of memory calls arranged in rows and columns and circuitry 208 for selectively performing logic operations on a bit of data stored in a selected call using a bit of received modifying data and a mode data bit for selecting a logic operation for performance. Circuitry 208 for modifying during an OR logic operation writing bit of the modifying data into the cell when the bit of modifying data is a logic one and maintaining an existing bit stored in call when the bit of modifying data is a logic zero. Memory system 104 further includes circuitry 207, 210 for receiving and latching the mode data and the modifying data through a single port.

    摘要翻译： 存储器系统104包括排列成行和列的存储器调用的阵列200和用于使用接收到的修改数据的位选择性地对存储在所选择的呼叫中的数据的位进行逻辑运算的逻辑运算，以及用于选择逻辑的模式数据位 操作性能。 当修改数据的位是逻辑1并且当修改数据的位为逻辑0时，保持存储在调用中的现有位，在修改数据的位的写入位期间将修改数据写入单元中的电路208。 存储器系统104还包括用于通过单个端口接收和锁存模式数据和修改数据的电路207,210。