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公开(公告)号：US08559249B1
公开(公告)日：2013-10-15
申请号：US13431424
申请日：2012-03-27
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
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2.发明授权Dual bank memory system with output multiplexing and methods using the same 失效具有输出多路复用的双行存储器系统及其使用方法
公开(公告)号：US5570320A
公开(公告)日：1996-10-29
申请号：US554297
申请日：1995-11-06
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/04 , G11C8/00
CPC分类号： G11C7/1021 , G11C7/00
摘要： A memory circuit 300 is provided which includes first and second banks 201a and 201b of memory cells arranged in rows and columns. Row decoder circuitry 210 is provided for selecting a row in at least one of the banks in response to row address. Row address circuitry 208, 209 is included for providing a sequence of row addresses to the row decoder circuitry in response to a single row address received at an address port to memory circuitry 300. Column decoder circuitry 213 is provided for selecting columns in each of the banks 201 in response to a column address. Column address circuitry 211, 212 is provided for presenting a sequence of column addresses to the column decoder circuitry in response to a single column address received at the address port.
摘要翻译： 提供存储电路300，其包括以行和列排列的存储单元的第一和第二存储体201a和201b。 行解码器电路210被提供用于响应于行地址来选择至少一个存储体中的行。 包括行地址电路208,209，用于响应于在存储器电路300的地址端口处接收到的单行地址，向行解码器电路提供行地址序列。列解码器电路213被提供用于在每个 银行201响应列地址。 列地址电路211,212被提供用于响应于在地址端口处接收到的单列地址，向列解码器电路呈现列地址序列。
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公开(公告)号：US5455526A
公开(公告)日：1995-10-03
申请号：US288442
申请日：1994-08-10
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/0175 , H03K19/094
CPC分类号： H03K3/356017 , H03K3/356113
摘要： A digital voltage shifter 101 is provided which includes an input buffer 200 having an input for receiving data logic high signals at a first voltage, a true output and a complementary output. A static random access memory cell 220 is also included which operates in response to a voltage supply providing a second voltage differing from the first voltage and having a first input coupled to the true output of the input buffer and a second input coupled to the complementary output of the input buffer. An output driver 230 is further included which operates in response to the second supply voltage and is coupled to an output of the memory cell, the output driver outputting the received logic signals at the second voltage.
摘要翻译： 提供数字电压转换器101，其包括具有用于在第一电压，真实输出和互补输出处接收数据逻辑高信号的输入的输入缓冲器200。 还包括静态随机存取存储器单元220，其响应于提供不同于第一电压的第二电压的电压供应并且具有耦合到输入缓冲器的真实输出的第一输入和耦合到互补输出的第二输入 的输入缓冲区。 还包括输出驱动器230，其响应于第二电源电压而操作并耦合到存储器单元的输出，输出驱动器以第二电压输出接收的逻辑信号。
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公开(公告)号：US08780657B2
公开(公告)日：2014-07-15
申请号：US13409399
申请日：2012-03-01
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C7/06 , G11C11/41 , G11C29/12 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.
摘要翻译： 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。
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公开(公告)号：US08780654B2
公开(公告)日：2014-07-15
申请号：US13443170
申请日：2012-04-10
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/12 , G11C11/41 , G11C11/419 , G11C29/12015 , G11C29/50
摘要： Embodiments of a memory are disclosed that may allow for the detection and compensation of weak data storage cells. The memory may include data storage cells, a selection circuit, a sense amplifier, and a timing and control block. The timing and control block may be operable to controllably select differing time periods between the activation of the selection circuit and the activation of the sense amplifier.
摘要翻译： 公开了可以允许弱数据存储单元的检测和补偿的存储器的实施例。 存储器可以包括数据存储单元，选择电路，读出放大器以及定时和控制块。 定时和控制块可操作以可控地选择激活选择电路和感测放大器的激活之间的不同时间段。
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公开(公告)号：US08555121B2
公开(公告)日：2013-10-08
申请号：US13026892
申请日：2011-02-14
IPC分类号： G01R31/28
CPC分类号： G06F11/2236 , G01R31/318541 , G01R31/318594
摘要： A scannable pulse dynamic logic gate may include an evaluation network that evaluates dynamic inputs in response to assertion of an evaluate pulse. The evaluate pulse may be generated from a clock signal such that it is shorter in duration than the clock signal. During a normal mode of operation, when the evaluate pulse is asserted, the evaluation network may discharge a dynamic node depending on the state of the dynamic inputs. The dynamic node may then drive output device(s). When the evaluate pulse is deasserted, the dynamic node may be precharged. The gate may also include scan input devices, which, during a scan mode of operation, may load scan input data onto the output node in response to assertion of a scan master clock. A storage element of the gate may receive and capture a value of the output node in response to assertion of a slave scan clock.
摘要翻译： 可扫描脉冲动态逻辑门可以包括评估网络，其评估响应于评估脉冲的断言的动态输入。 评估脉冲可以从时钟信号产生，使得其持续时间比时钟信号短。 在正常操作模式期间，当评估脉冲被断言时，评估网络可以根据动态输入的状态来放电动态节点。 然后动态节点可以驱动输出设备。 当评估脉冲无效时，可以对动态节点进行预充电。 门还可以包括扫描输入设备，其在扫描操作模式期间可以响应于扫描主时钟的断言将扫描输入数据加载到输出节点上。 响应于从属扫描时钟的断言，门的存储元件可以接收并捕获输出节点的值。
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公开(公告)号：US08482333B2
公开(公告)日：2013-07-09
申请号：US13274662
申请日：2011-10-17
IPC分类号： H03K3/01
CPC分类号： H03K5/08
摘要： A system and method for reducing power consumption within clock distribution on a semiconductor chip. A 4-phase clock generator within a clock distribution network provides 4 non-overlapping clock signals dependent upon a received input clock. A reduced voltage swing clock generator receives the non-overlapping clock signals and charges and discharges a second set of clock lines in a manner sequenced by the non-overlapping clock signals. The sequencing prevents a voltage range from reaching a magnitude equal to a power supply voltage for each of the second set of clock lines. In one embodiment, the magnitude reaches half of the power supply voltage. The reduced voltage swing latch receives the second set of clock lines. The reduced voltage swing latch updates and maintains logical state based at least upon the received second set of clock lines.
摘要翻译： 一种用于在半导体芯片上降低时钟分布内的功耗的系统和方法。 时钟分配网络内的4相时钟发生器根据接收到的输入时钟提供4个不重叠的时钟信号。 降低电压摆动时钟发生器接收不重叠的时钟信号，并以由非重叠时钟信号排序的方式对第二组时钟线进行充电和放电。 该顺序可防止电压范围达到等于第二组时钟线中的每一个的电源电压的幅度。 在一个实施例中，幅度达到电源电压的一半。 减小的电压摆动锁存器接收第二组时钟线。 至少基于所接收的第二组时钟线，减小的电压摆动锁存器更新并保持逻辑状态。
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8.发明授权Circuits, systems and methods for controlling substrate bias in integrated circuits 失效用于控制集成电路中的衬底偏置的电路，系统和方法
公开(公告)号：US5612644A
公开(公告)日：1997-03-18
申请号：US521891
申请日：1995-08-31
申请人： Michael E. Runas
发明人： Michael E. Runas
IPC分类号： G11C11/407 , G11C5/02 , G11C5/14 , G11C11/4074 , G05F1/10
CPC分类号： G11C5/025 , G11C11/4074 , G11C5/146
摘要： Substrate bias control circuitry 100 is provided which includes a bias sensor 101 for measuring a bias voltage of a substrate and generating a control signal and response. A master oscillator 102 is provided for generating a first driving signal, a frequency of the first driving signal adjusted by the control signal generated by the bias sensor 101. A first charge pump 103 is provided for pumping electrons into a substrate in response to the first driving signal. A slave oscillator generates a second driving signal, a frequency of the second driving signal is determined from the frequency of the first driving signal using a phase-locked loop. A second charge pump 105 is provided for pumping electrons into the substrate in response to the second driving signal.
摘要翻译： 提供了衬底偏置控制电路100，其包括用于测量衬底的偏置电压并产生控制信号和响应的偏置传感器101。 提供主振荡器102，用于产生第一驱动信号，由通过偏置传感器101产生的控制信号调节的第一驱动信号的频率。第一电荷泵103用于响应于第一驱动信号 驾驶信号。 从振荡器产生第二驱动信号，使用锁相环从第一驱动信号的频率确定第二驱动信号的频率。 提供第二电荷泵105以响应于第二驱动信号将电子泵送到衬底中。
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9.发明授权Circuits systems and methods for reducing power loss during transfer of data across a conductive line 失效用于在传输线路中传输数据时减少功率损耗的电路系统和方法
公开(公告)号：US5585744A
公开(公告)日：1996-12-17
申请号：US543210
申请日：1995-10-13
申请人： Michael E. Runas , Ronald T. Taylor
发明人： Michael E. Runas , Ronald T. Taylor
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/0013 , H03K19/018521
摘要： A line driver 202 is provided for transmitting signals across a line 201. Line driver 202 receives an input signal having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level.
摘要翻译： 线驱动器202被提供用于沿线201传输信号。线驱动器202接收具有在第一高电压电平和第一低电压电平之间的第一电压摆幅的输入信号。 线路驱动器202通过在线路201上传输具有大于第一低电压电平的第二低电压电平和小于第一高电压电平的第二高电压电平之间的第二电压摆幅的输出信号来减少线路201中的功率消耗。
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公开(公告)号：US09177671B2
公开(公告)日：2015-11-03
申请号：US13403543
申请日：2012-02-23
CPC分类号： G11C29/50 , G11C11/41 , G11C29/52 , G11C2029/5002
摘要： A memory that may allow for the detection of weak data storage cells may include data storage cells, a column multiplexer, a sense amplifier, and a load circuit. The load circuit may include one or more capacitive loads and may be operable to controllably select one or more of the capacitive loads to couple to the input of the sense amplifier.
摘要翻译： 可能允许检测弱数据存储单元的存储器可以包括数据存储单元，列多路复用器，读出放大器和负载电路。 负载电路可以包括一个或多个容性负载，并且可操作以可控制地选择一个或多个容性负载以耦合到读出放大器的输入端。
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