公开(公告)号：US5573979A

公开(公告)日：1996-11-12

申请号：US387509

申请日：1995-02-13

申请人： Robert Y. Tsu ,  Wei-Yung Hsu

发明人： Robert Y. Tsu ,  Wei-Yung Hsu

IPC分类号： C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92 ,  H01L21/44

CPC分类号： H01L21/32136 ,  H01L27/10852 ,  H01L28/40 ,  Y10S438/978

摘要： Generally, the present invention utilizes dry plasma etching techniques such as Electron Cyclotron Resonance (ECR) to produce sloped sidewalls on a DRAM storage cell. The rounded corners of the lower electrode made by this technique allow the advanced dielectric material to be deposited without substantial cracking, and it also allows the capacitance to be closely predicted and controlled due to the uniformity in which the advanced dielectric layer can be fabricated. One embodiment of the present invention is method of making a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises a barrier layer (e.g. TiN 36), and an unreactive layer (e.g. Pt 42).

摘要翻译： 通常，本发明利用诸如电子回旋共振（ECR）的干等离子体蚀刻技术在DRAM存储单元上产生倾斜的侧壁。 通过该技术制成的下电极的圆角允许先进的电介质材料沉积而没有实质的开裂，并且还可以由于可以制造高级介电层的均匀性来紧密地预测和控制电容。 本发明的一个实施例是制造微电子结构的方法，该微电子结构包括具有主表面的支撑层（例如Si衬底30），覆盖在支撑层的主表面上的下电极和高介电常数材料层（ 例如BST 44）覆盖在下电极的顶表面上。 下电极包括阻挡层（例如TiN 36）和非反应层（例如Pt 42）。

公开(公告)号：US06528888B2

公开(公告)日：2003-03-04

申请号：US09776212

申请日：2001-02-02

申请人： Chih-Chen Cho ,  Jeffrey A. McKee ,  William R. McKee ,  Isamu Asano ,  Robert Y. Tsu

发明人： Chih-Chen Cho ,  Jeffrey A. McKee ,  William R. McKee ,  Isamu Asano ,  Robert Y. Tsu

IPC分类号： H01L2348

CPC分类号： H01L27/10894 ,  H01L21/32051 ,  H01L21/32053 ,  H01L27/10811 ,  H01L27/10885

摘要： An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

摘要翻译： 集成电路。 电路包括存储单元阵列，其包括形成在基板上的字线201和位线200上形成的位线200和电容器203。 位线具有第一厚度和间距。 电路还包括阵列外围的电路，包括形成在衬底中的晶体管和晶体管上的导体202。 导体具有第二厚度和间距。 电路的特征还在于，位线和导体形成在公共导电层中。 在另外的实施例中，第一厚度和间距小于第二厚度和间距。