公开(公告)号：US4687988A

公开(公告)日：1987-08-18

申请号：US748288

申请日：1985-06-24

申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/277 ,  G06F17/50

CPC分类号： G01R31/318547 ,  G01R31/318385 ,  G01R31/318566 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

公开(公告)号：US4745355A

公开(公告)日：1988-05-17

申请号：US48178

申请日：1987-05-11

申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

IPC分类号： G01R31/3185 ,  G06F11/277 ,  G01R31/28

CPC分类号： G01R31/318566 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

摘要翻译： 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法和装置，通过将不同配置的伪随机图案序列并行地应用于被测设备的每个输入端，收集 并行地输出来自每个输出端子的响应，组合这些输出以获得作为并行输出的所有序列的预定函数的签名，并将测试签名与通过计算机模拟获得的已知的良好签名进行比较。 输入测试刺激以预定方式进一步改变为待测试设备的结构的函数，以单独加权输入以有利于更多或更少的二进制或零。

公开(公告)号：US3471415A

公开(公告)日：1969-10-07

申请号：US3471415D

申请日：1966-12-20

申请人： HONORA FRIEDMAN ,  ROGER N LANGMAID ,  DON E PICKART ,  IBM

发明人： FRIEDMAN HARRY

IPC分类号： C08L33/20 ,  C08L91/00 ,  C09D5/23 ,  C09D125/12 ,  H01F41/16 ,  C09D11/00 ,  C09D3/34 ,  H01F10/02

CPC分类号： H01F41/16 ,  C08L33/20 ,  C08L91/00 ,  C09D125/12 ,  C08L2666/02 ,  C08L2666/28 ,  C08L2666/54