公开(公告)号：US20080168318A1

公开(公告)日：2008-07-10

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30 ,  G06F11/00

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US07739573B2

公开(公告)日：2010-06-15

申请号：US11621766

申请日：2007-01-10

申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

IPC分类号： G01R31/30

CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

公开(公告)号：US4687988A

公开(公告)日：1987-08-18

申请号：US748288

申请日：1985-06-24

申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/277 ,  G06F17/50

CPC分类号： G01R31/318547 ,  G01R31/318385 ,  G01R31/318566 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

公开(公告)号：US4745355A

公开(公告)日：1988-05-17

申请号：US48178

申请日：1987-05-11

申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

IPC分类号： G01R31/3185 ,  G06F11/277 ,  G01R31/28

CPC分类号： G01R31/318566 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

摘要翻译： 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法和装置，通过将不同配置的伪随机图案序列并行地应用于被测设备的每个输入端，收集 并行地输出来自每个输出端子的响应，组合这些输出以获得作为并行输出的所有序列的预定函数的签名，并将测试签名与通过计算机模拟获得的已知的良好签名进行比较。 输入测试刺激以预定方式进一步改变为待测试设备的结构的函数，以单独加权输入以有利于更多或更少的二进制或零。