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10 条记录 (耗时 0.012 秒)

    Random pattern self test design
    2.
    发明授权
    Random pattern self test design 失效
    随机图案自检设计

    公开(公告)号：US4546473A

    公开(公告)日：1985-10-08

    申请号：US492288

    申请日：1983-05-06

    申请人： Edward B. Eichelberger ,  Eric Lindbloom

    发明人： Edward B. Eichelberger ,  Eric Lindbloom

    IPC分类号： G01R31/28 ,  H03K19/00 ,  H03K19/177

    CPC分类号： H03K19/1772

    摘要： A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.

    摘要翻译： 构建PLA来改进随机测试。 提供了分段电路，其允许禁用被称为段的输出线的部分，使得电路可以一次测试一个段。 还提供了选择电路，用于使产品术语行只能一次一个。 因此，虽然随机测试信号通常应用于PLA输入端子进行测试，但只有一小部分PLA能够进行测试。 随机生成选择电路的控制信号，使被测试的PLA的部分随机变化。

    Low signal margin detect circuit
    3.
    发明授权
    Low signal margin detect circuit 失效
    低信号余量检测电路

    公开(公告)号：US5396182A

    公开(公告)日：1995-03-07

    申请号：US955573

    申请日：1992-10-02

    申请人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

    发明人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

    IPC分类号： G01R31/26 ,  G01R31/28 ,  G01R31/30 ,  G06F11/22 ,  G01R1/04

    CPC分类号： G01R31/30 ,  G06F11/2273

    摘要： A low signal margin detect circuit for detecting reduced signal levels in differential current switch (DCS) or current switch emitter follower (CSEF) circuits. The circuit is connected to the outputs of a DCS circuit or to the output of a current switch emitter follower circuit and a reference voltage. A signal difference between the inputs is determined and, if less than an established amount, an error signal is generated. The detect circuit is enabled by a TESTBIAS signal. Two error signals are developed, ERRORX and ERRORY, which can be dotted with the error signals from adjacent circuits in the X and Y directions. This enables detection of the failing circuit through the use of appropriate error signal detection devices.

    摘要翻译： 用于检测差分电流开关（DCS）或电流开关射极跟随器（CSEF）电路中的降低的信号电平的低信号余量检测电路。 该电路连接到DCS电路的输出或电流开关射极跟随器电路的输出端和参考电压。 确定输入之间的信号差，并且如果小于建立的量，则产生误差信号。 检测电路由TESTBIAS信号使能。 出现两个错误信号ERRORX和ERRORY，可以在X和Y方向上点击相邻电路的错误信号。 这使得能够通过使用适当的误差信号检测装置来检测故障电路。

    Enhanced differential current switch compensating upshift circuit
    5.
    发明授权
    Enhanced differential current switch compensating upshift circuit 失效
    增强差动电流开关补偿升档电路

    公开(公告)号：US5274285A

    公开(公告)日：1993-12-28

    申请号：US940252

    申请日：1992-09-01

    申请人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

    发明人： David W. Boerstler ,  Edward B. Eichelberger ,  Gary T. Hendrickson ,  Charles B. Winn

    IPC分类号： H03K3/286 ,  H03K19/092 ,  H03K19/086

    CPC分类号： H03K3/286

    摘要： A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

    摘要翻译： 补偿升档电路提供低信号衰减，并以高速和低功率运行。 电容分流二极管交叉耦合两个晶体管的集电极和基极。 交叉耦合消除了升档电路中的信号摆幅恶化，并控制通过两个集电极电阻的电流。 均衡集电极电流消除了信号摆幅下降，同时提供了具有短延迟的升档电路。 电容器分流二极管可以由配置为提供必要的集电极基极电容的二极管连接的晶体管替代。

    Weighted random pattern testing apparatus and method
    7.
    发明授权
    Weighted random pattern testing apparatus and method 失效
    加权随机模式测试仪和方法

    公开(公告)号：US4801870A

    公开(公告)日：1989-01-31

    申请号：US151046

    申请日：1988-02-01

    申请人： Edward B. Eichelberger ,  Eric Lindbloom ,  Franco Motika ,  John A. Waicukauski

    发明人： Edward B. Eichelberger ,  Eric Lindbloom ,  Franco Motika ,  John A. Waicukauski

    IPC分类号： G01R31/3185 ,  G06F11/277 ,  G01R31/28

    CPC分类号： G06F11/277 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318566 ,  G01R31/31908 ,  G06F2201/83

    摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more of less binary ones or zeros.

    摘要翻译： 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法和装置，通过将不同配置的伪随机图案序列并行地应用于被测设备的每个输入端，收集 并行地输出来自每个输出端子的响应，组合这些输出以获得作为并行输出的所有序列的预定函数的签名，并将测试签名与通过计算机模拟获得的已知的良好签名进行比较。 输入测试刺激以预定方式进一步改变，作为待测试设备的结构的函数，以单独加权输入以有利于更少的二进制或零。

    Weighted random pattern testing apparatus and method
    9.
    发明授权
    Weighted random pattern testing apparatus and method 失效
    加权随机模式测试仪和方法

    公开(公告)号：US4745355A

    公开(公告)日：1988-05-17

    申请号：US48178

    申请日：1987-05-11

    申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

    发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

    IPC分类号： G01R31/3185 ,  G06F11/277 ,  G01R31/28

    CPC分类号： G01R31/318566 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

    摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

    摘要翻译： 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法和装置，通过将不同配置的伪随机图案序列并行地应用于被测设备的每个输入端，收集 并行地输出来自每个输出端子的响应，组合这些输出以获得作为并行输出的所有序列的预定函数的签名，并将测试签名与通过计算机模拟获得的已知的良好签名进行比较。 输入测试刺激以预定方式进一步改变为待测试设备的结构的函数，以单独加权输入以有利于更多或更少的二进制或零。

    Testing embedded arrays
    10.
    发明授权
    Testing embedded arrays 失效
    测试嵌入式阵列

    公开(公告)号：US3961252A

    公开(公告)日：1976-06-01

    申请号：US534606

    申请日：1974-12-20

    申请人： Edward B. Eichelberger

    发明人： Edward B. Eichelberger

    IPC分类号： G11C29/00 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/20 ,  G01R15/12

    CPC分类号： G01R31/318385 ,  G01R31/318544 ,  G11C29/02 ,  G11C29/20

    摘要： An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.

    摘要翻译： LSI半导体器件包括包含地址和数据寄存器的存储器阵列以及相关联的组合和/或顺序逻辑电路。 在存储器阵列不能从设备的输入和输出端子或焊盘全部或部分地直接访问的意义上，阵列是“嵌入”的。 为方便测试，地址寄存器和数据寄存器通过向寄存器的两个或更多位置添加一个“独占或”电路转换为计数器。 地址和数据寄存器通过其所有状态。 然后可将数据寄存器计数器输出与阵列输出进行比较，从而允许检查地址选择以及在每个存储位置写入或读取的能力。