公开(公告)号：US20120331240A1

公开(公告)日：2012-12-27

申请号：US13169128

申请日：2011-06-27

Applicant: Mirko Sauermann ,  Alexander Schackow ,  Cyprian Grassmann ,  Ulrich Hachmann ,  Ronalf Kramer ,  Dominik Langen ,  Wolfgang Raab

Inventor： Mirko Sauermann ,  Alexander Schackow ,  Cyprian Grassmann ,  Ulrich Hachmann ,  Ronalf Kramer ,  Dominik Langen ,  Wolfgang Raab

IPC: G06F12/00

CPC classification number: G06F15/167

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract translation: 用存储器和第一和第二数据处理部件描述数据处理装置。 第一数据处理部件包括控制存储器，对于存储器的多个存储区域的每个存储器区域，包括可以由第一数据处理部件和数据访问电路执行对存储器区域的数据访问的指示 被配置为如果可以由所述第一数据处理组件执行对所述存储器区域的数据访问，则对所述多个存储器区域的存储器区域执行数据访问; 以及设置电路，被配置为响应于完成第一数据处理组件的数据访问而将第一数据处理组件的存储器区域的数据访问设置为指示存储区域的数据访问可能不被第一数据处理组件执行， 存储区域。

公开(公告)号：US20060115056A1

公开(公告)日：2006-06-01

申请号：US10518321

申请日：2003-06-11

Applicant: Ronalf Kramer

Inventor： Ronalf Kramer

IPC: H04M1/24 ,  H04M3/22

CPC classification number: H04M3/30

Abstract: The invention relates to a method for detection of impedances, in particular along inductances, in telephone lines of the type with two metal wires as signal conductors (twisted pair), having the following method steps: a test signal in the form of an AC voltage is fed into the telephone line, a measurement signal of the reflection signal of the test signal is measured, which can be tapped off the input impedance of the entire line at the start of the line, the first method steps are carried out at a number of different frequencies within a preselected frequency range of the AC voltage of the test signal, the profile of the measurement signals is analyzed as a function of the frequency, with the derivative of the profile of the measurement signals being formed based on the frequency, at which point the second derivative of the profile of the measurement signals is formed based on the frequency, the profile of the second derivative of the profile of the measurement signals based on the frequency is investigated for one or more mathematical sign changes. The invention also relates to a method for qualification of telephone lines of the type with two metal wires as signal conductors (twisted pair) for suitability for data transmissions based on the DSL Standard, and to use of a DSL modem for carrying out methods such as this.

Abstract translation: 本发明涉及一种用于检测具有两条金属线作为信号导体（双绞线）类型的电话线路中的阻抗特别是电感的方法，具有以下方法步骤：以交流电压形式的测试信号 测量信号的反射信号的测量信号被测量，该测量信号可以在线路的起始处从整个线路的输入阻抗中抽出，第一个方法步骤以数字 在测试信号的AC电压的预选频率范围内的不同频率的不同频率，测量信号的分布作为频率的函数被分析，测量信号的分布的导数基于频率形成，在 这指出测量信号的轮廓的二阶导数基于频率形成，基于测量信号的测量信号的轮廓的二阶导数的轮廓 调查一个或多个数学符号变化的频率。 本发明还涉及一种用于使用两根金属线作为信号导体（双绞线）的电话线的鉴定方法，用于基于DSL标准的数据传输的适用性，并且使用DSL调制解调器来执行诸如 这个。

公开(公告)号：US08363764B2

公开(公告)日：2013-01-29

申请号：US11834433

申请日：2007-08-06

Applicant: Ronalf Kramer

Inventor： Ronalf Kramer

IPC: H04L7/00

CPC classification number: H04L7/033

Abstract: For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.

Abstract translation: 为了从异步发送的数据分组重构数据时钟，提供了包括受控振荡器的控制回路。 基于接收到的数据分组生成控制环路的输入信号。 在控制回路的信号路径中提供至少一个高通型滤波器。 数据同步输出的数据时钟是根据受控振荡器的输出信号生成的。

公开(公告)号：US20080112437A1

公开(公告)日：2008-05-15

申请号：US11560177

申请日：2006-11-15

Applicant: Ronalf Kramer ,  Stefan Honken

Inventor： Ronalf Kramer ,  Stefan Honken

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract translation: 在数据网络的入口接口生成第一信息数据，在数据网络的出口接口生成第二信息数据时，根据第二信息数据生成校正数据，在出口接口，时钟频率为 基于第一信息数据和校正数据恢复。

公开(公告)号：US08880811B2

公开(公告)日：2014-11-04

申请号：US13169128

申请日：2011-06-27

Applicant: Mirko Sauermann ,  Alexander Schackow ,  Cyprian Grassmann ,  Ulrich Hachmann ,  Ronalf Kramer ,  Dominik Langen ,  Wolfgang Raab

Inventor： Mirko Sauermann ,  Alexander Schackow ,  Cyprian Grassmann ,  Ulrich Hachmann ,  Ronalf Kramer ,  Dominik Langen ,  Wolfgang Raab

IPC: G06F12/00 ,  G06F15/167

CPC classification number: G06F15/167

Abstract: A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Abstract translation: 用存储器和第一和第二数据处理部件描述数据处理装置。 第一数据处理部件包括控制存储器，对于存储器的多个存储区域的每个存储器区域，包括可以由第一数据处理部件和数据访问电路执行对存储器区域的数据访问的指示 被配置为如果可以由所述第一数据处理组件执行对所述存储器区域的数据访问，则对所述多个存储器区域的存储器区域执行数据访问; 以及设置电路，被配置为响应于完成第一数据处理组件的数据访问而将第一数据处理组件的存储器区域的数据访问设置为指示存储区域的数据访问可能不被第一数据处理组件执行， 存储区域。

公开(公告)号：US07843946B2

公开(公告)日：2010-11-30

申请号：US11560177

申请日：2006-11-15

Applicant: Ronalf Kramer ,  Stefan Honken

Inventor： Ronalf Kramer ,  Stefan Honken

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: At an ingress interface of a data network first information data are generated, at an egress interface of the data network second information data are generated, correction data are generated on the basis of the second information data, and at the egress interface a clock frequency is recovered on the basis of the first information data and the correction data.

Abstract translation: 在数据网络的入口接口生成第一信息数据，在数据网络的出口接口生成第二信息数据时，根据第二信息数据生成校正数据，在出口接口，时钟频率为 基于第一信息数据和校正数据恢复。

公开(公告)号：US08363559B2

公开(公告)日：2013-01-29

申请号：US11526541

申请日：2006-09-25

Applicant: Stefan Honken ,  Ronalf Kramer

Inventor： Stefan Honken ,  Ronalf Kramer

IPC: H03D3/24

CPC classification number: H04J3/0664 ,  H03L7/0805 ,  H03L7/093 ,  H03L7/0994 ,  H04J3/1623

Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract translation: 一种用于通过数据网络提供用于恢复时钟频率的信息的方法和系统包括通过在数据网络的入口接口处使用数字锁相环来产生表示时钟频率与参考频率之间的频率差的值 通过数据网络发送生成的值，并通过使用参考频率和发送的值来恢复数据网络的出口接口处的时钟频率。 还公开了其它系统和方法。

公开(公告)号：US20090041028A1

公开(公告)日：2009-02-12

申请号：US11834433

申请日：2007-08-06

Applicant: Ronalf Kramer

Inventor： Ronalf Kramer

IPC: H04L12/56

CPC classification number: H04L7/033

Abstract: For reconstructing a data clock from asynchronously transmitted data packets, a control loop is provided which includes a controlled oscillator. An input signal of the control loop is generated on the basis of the received data packets. At least one high-pass type filter is provided in a signal path of the control loop. The data clock for the synchronous output of data is generated on the basis of an output signal of the controlled oscillator.

Abstract translation: 为了从异步发送的数据分组重构数据时钟，提供了包括受控振荡器的控制回路。 基于接收到的数据分组生成控制环路的输入信号。 在控制回路的信号路径中提供至少一个高通型滤波器。 数据同步输出的数据时钟是根据受控振荡器的输出信号生成的。

公开(公告)号：US20080075220A1

公开(公告)日：2008-03-27

申请号：US11526541

申请日：2006-09-25

Applicant: Stefan Honken ,  Ronalf Kramer

Inventor： Stefan Honken ,  Ronalf Kramer

IPC: H03D3/24

CPC classification number: H04J3/0664 ,  H03L7/0805 ,  H03L7/093 ,  H03L7/0994 ,  H04J3/1623

Abstract: A method and a system for providing information for recovering a clock frequency via a data network comprise generating a value representative of a frequency difference between a clock frequency and a reference frequency by using a digital phase-locked loop at an ingress interface of a data network, transmitting the generated value over the data network, and recovering the clock frequency at an egress interface of the data network by using the reference frequency and the transmitted value. Other systems and methods are also disclosed.

Abstract translation: 一种用于通过数据网络提供用于恢复时钟频率的信息的方法和系统包括通过在数据网络的入口接口处使用数字锁相环来产生表示时钟频率与参考频率之间的频率差的值 通过数据网络发送生成的值，并通过使用参考频率和发送的值来恢复数据网络的出口接口处的时钟频率。 还公开了其它系统和方法。

公开(公告)号：US5864581A

公开(公告)日：1999-01-26

申请号：US711021

申请日：1996-09-09

Applicant: Michael Alger-Meunier ,  Yousif Ammar ,  Ronalf Kramer

Inventor： Michael Alger-Meunier ,  Yousif Ammar ,  Ronalf Kramer

IPC: G01R29/00 ,  G06F1/10 ,  G06F11/24 ,  H04B3/462 ,  H04L7/00 ,  H04L25/02 ,  H04B17/00 ,  H04B17/02 ,  H04M1/24 ,  H04Q7/00

CPC classification number: H04B3/462 ,  G06F11/24

Abstract: A signal transmission apparatus includes a higher-level station, a lower-level station and a digital transmission device connected between the stations and having a signal transit time to be measured. Each of the stations has a transmitter for sending useful signals, each clocked by a respective clock signal, through the transmission device to other station. Each of the stations has a receiver for receiving the useful signals clocked by the other station and for separating out the clock signal superimposed on the applicable useful signal. The useful signal to be transmitted in the higher-level station is clocked by a given clock signal. The useful signal to be transmitted in the lower-level station is clocked by a clock signal derived from the clock signal separated out from the receiver of the lower-level station. The higher-level station has a phase comparator for comparing the given clock signal with the clock signal separated out by the receiver of the higher-level station and supplying a comparison outcome. The higher-level station has an arithmetic unit for calculating the signal transit time from the comparison outcome.

Abstract translation: 信号传输装置包括连接在站之间并具有要测量的信号传播时间的较高级站，较低级站和数字传输装置。 每个站具有用于发送有用信号的发射机，每个时钟由各自的时钟信号通过传输设备发送到其他站。 每个站具有接收器，用于接收由另一个站所计时的有用信号，并且用于分离叠加在适用的有用信号上的时钟信号。 要在上位站发送的有用信号由给定的时钟信号计时。 要在下位站发送的有用信号由从下层站的接收机分离的时钟信号得到的时钟信号计时。 上级电台具有一个相位比较器，用于将给定的时钟信号与由上级电台的接收器分离的时钟信号进行比较，并提供比较结果。 上位站具有用于从比较结果计算信号传播时间的算术单元。