摘要:
A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.
摘要:
The number of response-waiting requests which are already sent to a server (4) but to which a response is not yet returned from the server (4) is limited. To limit this number, received requests are temporarily accumulated in a buffer if the number of response-waiting requests has reached a threshold and, until the number of response-waiting requests falls below the threshold, requests are not sent from the buffer. The execution status of the server (4) is monitored, and the threshold is increased when the response time from the server (4) to a request is within an allowable range, and the threshold is decreased when the response time exceeds the allowable range. In addition, TCP connections between a load control device (3) and clients (1-1, . . . , 1-n) are aggregated so that the number of simultaneous connections of TCP connections between the server (4) and the load control device (3) becomes equal to or smaller than the threshold of the number of response-waiting requests.
摘要:
The number of response-waiting requests which are already sent to a server (4) but to which a response is not yet returned from the server (4) is limited. To limit this number, received requests are temporarily accumulated in a buffer if the number of response-waiting requests has reached a threshold and, until the number of response-waiting requests falls below the threshold, requests are not sent from the buffer. The execution status of the server (4) is monitored, and the threshold is increased when the response time from the server (4) to a request is within an allowable range, and the threshold is decreased when the response time exceeds the allowable range. In addition, TCP connections between a load control device (3) and clients (1-1, 1-n) are aggregated so that the number of simultaneous connections of TCP connections between the server (4) and the load control device (3) becomes equal to or smaller than the threshold of the number of response-waiting requests.
摘要:
A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instruction from an instruction memory based on an input packet or a program counter; an instruction decode unit which decodes the issued instruction and, in the case of the control-driven instruction, thereafter accesses a register and performs register renaming if a data hazard is detected; a firing control unit which stores the decoded instruction in a matching memory to wait therein, and which selects one of the ready-to-fire instructions and fires the selected instruction; an execution unit which performs an operation specified by the fired instruction and, in the case of the data-driven instruction, transfers an operation result to the instruction fetch unit, or in the case of the control-driven instruction, forwards the operation result to the firing control unit; and a write back unit which writes the operation result to a register.
摘要:
An emulation system for data-driven processors aims at shortening the emulation time by employing parallel processing techniques without increasing overhead. The emulation system emulates virtual data-driven processors by using real data-driven processors. The emulation is performed by dividing the functionality of the processor into a data path and a timing path. In the data path emulation, each virtual packet to be processed in the virtual processor is expressed as a PACKET message, and the processing operation of the virtual packet is evaluated for each functional block. In the timing path emulation, a SEND signal and an ACK signal, to be controlled by a self-timed transfer control mechanism and a gate logic, are expressed as a SEND message and an ACK message, respectively, and stage-to-stage transfer operations of the SEND signal and the ACK signal are evaluated.