公开(公告)号：US08821037B2

公开(公告)日：2014-09-02

申请号：US13118053

申请日：2011-05-27

申请人： Kazushige Oki ,  Hirokazu Komachi ,  Takahisa Wada

发明人： Kazushige Oki ,  Hirokazu Komachi ,  Takahisa Wada

IPC分类号： G02B6/42

CPC分类号： G02B6/4292 ,  G02B6/3821 ,  G02B6/3825 ,  G02B6/3878 ,  G02B6/3897 ,  G02B6/4201 ,  G02B6/421 ,  G02B6/4243 ,  G02B6/4246 ,  G02B6/4256 ,  G02B6/4261 ,  G02B6/4274 ,  G02B6/4277 ,  G02B6/428 ,  G02B6/4284 ,  Y10T29/49002 ,  Y10T29/49826

摘要： A pluggable optical transceiver is disclosed. The transceiver comprises a plurality of OSAs, an optical member and a plurality of inner fibers to couple the optical member with OSAs. The inner fibers each provides an inner connector to couple with one of OSAs. The housing, which installs the OSAs, the optical member and the inner fiber, is made of metal and has a grooves into which the inner fibers is set so as to arrange them orderly.

摘要翻译： 公开了一种可插拔光收发器。 收发器包括多个OSA，光学构件和多个内部光纤，以将光学构件与OSA耦合。 内部纤维各自提供内部连接器以与OSA之一耦合。 安装OSA，光学构件和内部光纤的壳体由金属制成，并且具有凹槽，内部纤维被设置在其中以便有序地布置。

公开(公告)号：US08345113B2

公开(公告)日：2013-01-01

申请号：US12512593

申请日：2009-07-30

申请人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Keiri Nakanishi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Masato Sumiyoshi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： H04N5/228

CPC分类号： H04N5/77 ,  G06F9/30043 ,  G06F9/35 ,  G06F9/355

摘要： An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

摘要翻译： 图像处理装置具有：数据存储器，被配置为存储图像数据; RP寄存器，被配置为保存指示图像数据的帧中的RP的位置的二维地址; 以及RP控制部，被配置为基于帧的宽度和高度来控制由RP寄存器保持的二维地址。 此外，图像处理装置具有地址计算单元，其被配置为当基于具有用于通过组合从RP指定二维相对位置的字段的指令代码从数据存储器读取目标像素数据时， 基于二维地址，立即值的组合和帧的宽度，计算存储读取目标像素数据的地址。

公开(公告)号：US20100110289A1

公开(公告)日：2010-05-06

申请号：US12540798

申请日：2009-08-13

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G06T1/00 ,  H04N5/04

CPC分类号： G06T1/20

摘要： An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

摘要翻译： 图像处理器包括对输入像素数据的数量进行计数的视频输入单元，并且命令获取/发出单元计算包括关于相对位置寄存器的信息的命令，其中从输入像素数据到执行命令的延迟量 取出存储的像素位置，基于延迟量的处理对象像素数据的像素位置和计数结果，并且基于计算出的像素位置确定是否应执行信号处理或指定算术运算中使用的操作数。

公开(公告)号：US08730250B2

公开(公告)日：2014-05-20

申请号：US12540798

申请日：2009-08-13

申请人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

发明人： Yasuki Tanabe ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Ryuji Hada

IPC分类号： G09G5/02

CPC分类号： G06T1/20

摘要： An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

摘要翻译： 图像处理器包括对输入像素数据的数量进行计数的视频输入单元，并且命令获取/发出单元计算包括关于相对位置寄存器的信息的命令，其中从输入像素数据到执行命令的延迟量 取出存储的像素位置，基于延迟量的处理对象像素数据的像素位置和计数结果，并且基于计算出的像素位置确定是否应执行信号处理或指定算术运算中使用的操作数。

公开(公告)号：US20120249152A1

公开(公告)日：2012-10-04

申请号：US13431739

申请日：2012-03-27

申请人： Yasuyuki NISHIBAYASHI ,  Yoshihiro Oba ,  Kotaro Ise ,  Keiichi Teramoto ,  Takahisa Wada

发明人： Yasuyuki NISHIBAYASHI ,  Yoshihiro Oba ,  Kotaro Ise ,  Keiichi Teramoto ,  Takahisa Wada

IPC分类号： G01N27/417

CPC分类号： H02J7/0063 ,  G01R31/371 ,  H02J3/38 ,  H02J7/0068 ,  H02J7/35 ,  H02J13/0062 ,  Y02E40/72 ,  Y04S10/12 ,  Y04S10/123

摘要： According to one exemplary embodiment, a charging/discharging determination apparatus includes: a receiving module which receives information of a rated capacity of a battery; and a determination module which determines that charging or a discharge of the battery is permitted if an absolute value of a difference between the rated capacity and a measured capacity which is an actual capacity of the battery is within a threshold value.

摘要翻译： 根据一个示例性实施例，充电/放电确定装置包括：接收模块，其接收电池的额定容量的信息; 以及如果所述额定容量和作为所述电池的实际容量的测量容量之间的差的绝对值在阈值内，则确定允许所述电池的充电或放电的确定模块。

公开(公告)号：US08176290B2

公开(公告)日：2012-05-08

申请号：US12482876

申请日：2009-06-11

申请人： Takahisa Wada ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

发明人： Takahisa Wada ,  Katsuyuki Kimura ,  Shunichi Ishiwata ,  Takashi Miyamori ,  Ryuji Hada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Masato Sumiyoshi

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F15/76 ,  G06F7/00 ,  G06F17/00

CPC分类号： G06F9/342 ,  G06F12/1441

摘要： A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

摘要翻译： 存储器控制器在接收到将写入数据写入由处理器发出的第二存储器区域的地址的写入请求时，确定由处理器请求从第一存储器区域的地址请求的读取数据是否与 写入数据被请求写入第二存储器区域的地址，并且如果读取数据与写入数据匹配，则防止将写入数据写入第二存储器区域的地址。

公开(公告)号：US20100211758A1

公开(公告)日：2010-08-19

申请号：US12648769

申请日：2009-12-29

申请人： Masato Sumiyoshi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Ryuji Hada

发明人： Masato Sumiyoshi ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Yasuki Tanabe ,  Ryuji Hada

IPC分类号： G06F9/312 ,  G06F9/445 ,  G06F9/46 ,  G06F12/00 ,  G06F9/34

CPC分类号： G06F9/383 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/345

摘要： A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

摘要翻译： 可以在数据阵列单元中执行顺序处理的微处理器包括：加载存储单元，当获取的指令是数据的加载指令时，加载来自存储器宽度单元中的数据存储器的指定数据的数据序列，并基于 该指令的分析结果，将来被安排在加载指令中指定的数据; 以及数据临时存储单元，其将使用调度数据存储为由所述加载存储单元指定的数据。

公开(公告)号：US20100030978A1

公开(公告)日：2010-02-04

申请号：US12511305

申请日：2009-07-29

申请人： Ryuji HADA ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Yasuki Tanabe

发明人： Ryuji HADA ,  Takashi Miyamori ,  Shunichi Ishiwata ,  Katsuyuki Kimura ,  Takahisa Wada ,  Keiri Nakanishi ,  Masato Sumiyoshi ,  Yasuki Tanabe

IPC分类号： G06F12/00

CPC分类号： H04L49/901 ,  G09G5/42

摘要： A memory controller controls a memory access to each memory region out of one or more memory regions in SIMD unit. The memory controller includes: a pointer-calculation hardware unit that increments by unit SIMD a value of an access control pointer corresponding to each of the memory regions at different timings corresponding to an access mode set beforehand in each memory region; and a memory-access-control hardware unit that calculates an access destination address in each of the memory regions based on a value of an access control pointer in the memory region, and causes a memory access in SIMD unit to be performed to the calculated access destination address.

摘要翻译： 存储器控制器控制对SIMD单元中的一个或多个存储器区域中的每个存储器区域的存储器访问。 存储器控制器包括：指针计算硬件单元，其以与每个存储器区域中预先设置的访问模式相对应的不同定时，以单位SIMD为单位增加与每个存储区域对应的访问控制指针的值; 以及存储器访问控制硬件单元，其基于存储区域中的访问控制指针的值来计算每个存储器区域中的访问目的地地址，并且使SIMD单元中的存储器访问对所计算的访问执行 目的地址。

公开(公告)号：US20060198444A1

公开(公告)日：2006-09-07

申请号：US11365525

申请日：2006-03-02

申请人： Takahisa Wada

发明人： Takahisa Wada

IPC分类号： H04N11/02 ,  H04N11/04 ,  H04N7/12 ,  H04B1/66

CPC分类号： H04N19/61 ,  H04N19/51 ,  H04N19/513 ,  H04N19/56

摘要： A moving picture processor includes a first detector configured to detect a reference block most similar to a target block for which motion is to be detected and which is set in a current picture, and to generate a first motion vector candidate indicating a relative position between the target block and the reference block. A second detector is configured to detect a first reference area most similar to a first target area obtained by combining the target block and a first adjacent block adjacent to the target block, and to generate a second motion vector candidate indicating a relative position between the first target area and the first reference area. A determination circuit is configured to determine a motion vector for the target block, based on the first and second motion vector candidates.

摘要翻译： 运动图像处理器包括：第一检测器，被配置为检测与要检测运动的目标块最相似的参考块，并且其被设置在当前图像中;以及生成第一运动矢量候选， 目标块和参考块。 第二检测器被配置为检测与通过组合目标块和与目标块相邻的第一相邻块获得的第一目标区域最相似的第一参考区域，并且生成指示第一和第二目标区域之间的相对位置的第二运动向量候选 目标区域和第一参考区域。 确定电路被配置为基于第一和第二运动矢量候选来确定目标块的运动矢量。

公开(公告)号：US20130009607A1

公开(公告)日：2013-01-10

申请号：US13611315

申请日：2012-09-12

申请人： Yasuyuki NISHIBAYASHI ,  Takahisa WADA ,  Kotaro ISE ,  Keiichi TERAMOTO ,  Yusuke DOI ,  Yoshiki TERASHIMA

发明人： Yasuyuki NISHIBAYASHI ,  Takahisa WADA ,  Kotaro ISE ,  Keiichi TERAMOTO ,  Yusuke DOI ,  Yoshiki TERASHIMA

IPC分类号： H02J7/04 ,  G06F19/00

CPC分类号： B60L53/63 ,  H02J3/14 ,  H02J7/00 ,  Y02E60/721 ,  Y02T10/7005 ,  Y02T10/7072 ,  Y02T90/121 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/163 ,  Y04S10/126

摘要： A determination determines permission/forbiddance to charge an accumulator that obtains electrical power from a power grid network. The determination device comprises a first acquisition unit configured to acquire first information about a requested power amount requested to charge the accumulator, a second acquisition unit configured to acquire second information about an available power amount that can be provided from the power grid network, and a determination unit configured to determine permission or forbiddance with respect to the accumulator based on the first information and the second information.

摘要翻译： 确定对从电网网络获得电力的蓄电池充电的允许/禁止。 确定装置包括：第一获取单元，被配置为获取关于请求对蓄电池充电的请求电力量的第一信息;第二获取单元，被配置为获取关于可从电网网络提供的可用功率量的第二信息;以及 确定单元，被配置为基于所述第一信息和所述第二信息来确定关于所述累加器的允许或禁止。