公开(公告)号：US20090287893A1

公开(公告)日：2009-11-19

申请号：US12122568

申请日：2008-05-16

申请人： CHUANG CHENG ,  SHIH CHIEH TAI ,  MING HUI LIN ,  CHIH NAN YEN ,  FUJA SHONE

发明人： CHUANG CHENG ,  SHIH CHIEH TAI ,  MING HUI LIN ,  CHIH NAN YEN ,  FUJA SHONE

IPC分类号： G06F12/12

CPC分类号： G06F12/0246 ,  G06F11/141

摘要： A method is employed to manage a memory, e.g., a flash memory, including a plurality of paired pages. Each paired page includes a page and a respective risk zone. For each write command, at least one unwritten page is selected for writing new data. For each unwritten page whose risk zone includes at least one written page, each written page is copied or backed up, and the new data is written to the unwritten page. For each unwritten page whose risk zone lacks a written page, the new data is written to the unwritten page. In an embodiment, the written page is copied only if the unwritten page and the written page are operated by different write commands.

摘要翻译： 采用一种方法来管理包括多个配对页面的存储器，例如闪速存储器。 每个配对页面包括页面和相应的风险区域。 对于每个写入命令，至少选择一个未写入的页面来写入新数据。 对于每个未写入的页面，其风险区域至少包含一个写入页面，每个写入的页面都将被复制或备份，并将新数据写入未写入的页面。 对于其风险区缺少书面页面的每个未写入页面，新数据将写入未​​写入的页面。 在一个实施例中，仅当未写入的页面和写入的页面由不同的写入命令操作时才复制书面页面。

公开(公告)号：US20090106513A1

公开(公告)日：2009-04-23

申请号：US11875952

申请日：2007-10-22

申请人： Chuang Cheng ,  Chih-Wei Tsai ,  Shih-Chieh Tai ,  Satoshi Sugawa ,  Wen-Lin Cheng

发明人： Chuang Cheng ,  Chih-Wei Tsai ,  Shih-Chieh Tai ,  Satoshi Sugawa ,  Wen-Lin Cheng

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/1068 ,  G06F2212/1032

摘要： A method for copying data in a non-volatile memory system is disclosed. The method includes calculating a number of errors of a first set of data from a source block of the non-volatile memory saved in the buffer of the controller, transmitting the first set of data saved in the buffer of the controller to a buffer of the non-volatile memory when the number of errors is lower than a threshold, and programming a destination block of the non-volatile memory with the first set of data saved in the buffer of the non-volatile memory when the number of errors is lower than the threshold.

摘要翻译： 公开了一种在非易失性存储器系统中复制数据的方法。 该方法包括从存储在控制器的缓冲器中的非易失性存储器的源块中计算第一组数据的错误数量，将保存在控制器的缓冲器中的第一组数据发送到控制器的缓冲器 当错误数量低于阈值时，非易失性存储器，并且当错误数量低于非易失性存储器的数量时，利用保存在非易失性存储器的缓冲器中的第一组数据来编程非易失性存储器的目的地块 门槛。

公开(公告)号：US08032690B2

公开(公告)日：2011-10-04

申请号：US12024149

申请日：2008-02-01

申请人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

发明人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0634 ,  G06F1/3221 ,  G06F1/3268 ,  G06F3/0625 ,  G06F3/0679 ,  Y02D10/154 ,  Y02D50/20

摘要： A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

摘要翻译： 提供非易失性存储器件，以及用于访问非易失性存储器件的方法。 非易失性存储器件通过总线连接到主机。 非易失性存储器件包括MCU。 通过仅使用辅助电路独立处理特定命令，MCU可以停止工作，从而节省电力。 通过在非易失性存储器件忙时将总线设置为省电模式，主机和非易失性存储器件将不会相互通信，从而节省电力。

公开(公告)号：US20090254729A1

公开(公告)日：2009-10-08

申请号：US12098741

申请日：2008-04-07

申请人： CHIEN CHENG LIN ,  HSIN JEN HUANG ,  SHIH CHIEH TAI ,  CHIH NAN YEN ,  FUJA SHONE

发明人： CHIEN CHENG LIN ,  HSIN JEN HUANG ,  SHIH CHIEH TAI ,  CHIH NAN YEN ,  FUJA SHONE

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7207 ,  G06F2212/7211

摘要： According to the method of wear leveling for a non-volatile memory of the present invention, the non-volatile memory is divided into a plurality of windows, and a mapping table is built in which the logical block addresses having frequently accessed data are allocated equally to the plurality of windows. The logical block addresses may store a File Allocation Table (FAT) or a directory table; therefore the windows they locate will be written or erased more frequently. In an embodiment, the logical block addresses having frequently accessed data are allocated on a one-to-one basis to the plurality of windows. For example, the plurality of windows may comprise Windows 0, 1, 2 and 3, the logical block addresses comprise logical block addresses 0, 1, 2 and 3, and logical block addresses 0, 1, 2 and 3 point to Windows 0, 1, 2 and 3, respectively.

摘要翻译： 根据本发明的非易失性存储器的磨损均衡方法，将非易失性存储器划分为多个窗口，并且构建了具有频繁访问的数据的逻辑块地址被均等地分配的映射表 到多个窗口。 逻辑块地址可以存储文件分配表（FAT）或目录表; 因此，他们找到的窗口将被更频繁地写入或擦除。 在一个实施例中，具有频繁访问的数据的逻辑块地址被分配给多个窗口。 例如，多个窗口可以包括Windows 0,1,2和3，逻辑块地址包括逻辑块地址0,1,2和3，逻辑块地址0,1,2和3指向Windows 0， 分别为1,2和3。

公开(公告)号：US20080183947A1

公开(公告)日：2008-07-31

申请号：US11668469

申请日：2007-01-30

申请人： Fuja Shone ,  Shih-Chieh Tai

发明人： Fuja Shone ,  Shih-Chieh Tai

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hierarchical mechanism for preventing concentrated wear on single physical block or a specific set of physical blocks in the physical memory is proposed. The logical blocks mapping to the physical blocks in the physical memory are classified into two different levels for implicitly representing the modification times of the physical blocks. A modify count and a maximum modify count are further included for counting the modification times in a single process of the hierarchical mechanism and for limiting the modification times in single process, leading to the probabilities of all the physical blocks being modified in the physical memory being balanced. The breakdown of the physical memory caused by the breakdown of a specific set of physical blocks or single physical block is thus prevented.

摘要翻译： 提出了一种用于防止物理存储器中单个物理块或特定物理块集合磨损的分级机制。 映射到物理存储器中的物理块的逻辑块被分类为两个不同的级别，用于隐含地表示物理块的修改时间。 还包括修改计数和最大修改计数，用于对分级机制的单个进程中的修改时间进行计数，并且在单个进程中限制修改时间，导致在物理存储器中修改的所有物理块的概率为 均衡。 因此防止了由特定的一组物理块或单个物理块的故障引起的物理存储器的故障。

公开(公告)号：US08140737B2

公开(公告)日：2012-03-20

申请号：US11668469

申请日：2007-01-30

申请人： Fuja Shone ,  Shih-Chieh Tai

发明人： Fuja Shone ,  Shih-Chieh Tai

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： A hierarchical mechanism for preventing concentrated wear on single physical block or a specific set of physical blocks in the physical memory is proposed. The logical blocks mapping to the physical blocks in the physical memory are classified into two different levels for implicitly representing the modification times of the physical blocks. A modify count and a maximum modify count are further included for counting the modification times in a single process of the hierarchical mechanism and for limiting the modification times in single process, leading to the probabilities of all the physical blocks being modified in the physical memory being balanced. The breakdown of the physical memory caused by the breakdown of a specific set of physical blocks or single physical block is thus prevented.

摘要翻译： 提出了一种用于防止物理存储器中单个物理块或特定物理块集合磨损的分级机制。 映射到物理存储器中的物理块的逻辑块被分类为两个不同的级别，用于隐含地表示物理块的修改时间。 还包括修改计数和最大修改计数，用于对分级机制的单个进程中的修改时间进行计数，并且在单个进程中限制修改时间，导致在物理存储器中修改的所有物理块的概率为 均衡。 因此防止了由特定的一组物理块或单个物理块的故障引起的物理存储器的故障。

公开(公告)号：US08090898B2

公开(公告)日：2012-01-03

申请号：US12153908

申请日：2008-05-28

申请人： Chung-Chiang Chew ,  Shih-Chieh Tai ,  Chin-Nan Yen ,  Fu-Ja Shone

发明人： Chung-Chiang Chew ,  Shih-Chieh Tai ,  Chin-Nan Yen ,  Fu-Ja Shone

IPC分类号： G06F12/00

CPC分类号： G11C16/16

摘要： A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.

摘要翻译： 非易失性存储器系统具有连接到存储介质和多个非易失性存储器芯片的控制器芯片。 存储介质存储用于控制器芯片的程序代码，以随着时间的推移分配非易失性存储器芯片的操作，从而分散由操作引起的峰值电流，从而提高系统的稳定性。

公开(公告)号：US20090198919A1

公开(公告)日：2009-08-06

申请号：US12024149

申请日：2008-02-01

申请人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

发明人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

IPC分类号： G06F12/00

CPC分类号： G06F3/0634 ,  G06F1/3221 ,  G06F1/3268 ,  G06F3/0625 ,  G06F3/0679 ,  Y02D10/154 ,  Y02D50/20

摘要： A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

摘要翻译： 提供非易失性存储器件，以及用于访问非易失性存储器件的方法。 非易失性存储器件通过总线连接到主机。 非易失性存储器件包括MCU。 通过仅使用辅助电路独立处理特定命令，MCU可以停止工作，从而节省电力。 通过在非易失性存储器件忙时将总线设置为省电模式，主机和非易失性存储器件将不会相互通信，从而节省电力。

公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

申请人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

发明人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

摘要翻译： 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

申请人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

发明人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC分类号： G06F13/12 ,  G06F12/02

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

摘要翻译： 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。