公开(公告)号：US08332607B2

公开(公告)日：2012-12-11

申请号：US12183229

申请日：2008-07-31

申请人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

发明人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

摘要翻译： 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US08095724B2

公开(公告)日：2012-01-10

申请号：US12026400

申请日：2008-02-05

申请人： Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

发明人： Yung Li Ji ,  Chia Chen Chang ,  Chih Nan Yen ,  Fuja Shone

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0246 ,  C07D401/12 ,  G06F2212/7201 ,  G06F2212/7211

摘要： A method of wear leveling for a non-volatile memory is disclosed. A non-volatile memory is divided into windows and gaps, with each gap between two adjacent windows. The windows comprise physical blocks mapped to logical addresses, and the gaps comprise physical blocks not mapped to logical addresses. The windows are shifted through the non-volatile memory in which the mapping to the physical blocks in the window to be shifted is changed to the physical blocks in the gap.

摘要翻译： 公开了一种用于非易失性存储器的磨损均衡的方法。 非易失性存储器分为窗口和间隙，两个相邻窗口之间的每个间隙。 窗口包括映射到逻辑地址的物理块，并且间隙包括未映射到逻辑地址的物理块。 窗口移动通过非易失性存储器，在该非易失性存储器中，将要移位的窗口中的物理块的映射改变为间隙中的物理块。

公开(公告)号：US20100293309A1

公开(公告)日：2010-11-18

申请号：US12465552

申请日：2009-05-13

申请人： Yun-Ching Lin ,  Chih-Cheng Tu ,  Chih-Hwa Chang ,  Yung-Li Ji ,  Fu-Chen Cheng

发明人： Yun-Ching Lin ,  Chih-Cheng Tu ,  Chih-Hwa Chang ,  Yung-Li Ji ,  Fu-Chen Cheng

IPC分类号： G06F13/42

CPC分类号： G06F13/4081

摘要： A production tool for low-level format of a storage device is disclosed. The production tool includes an input connector connectable and an output connector, both of which conform to an interface standard. At least a redundant pin of the input connector is unconnected with a corresponding redundant pin of the output connector, and the redundant pin of the output connector is electrically connected to receive a provided predetermined signal, the presence of which indicating a low-level format mode.

摘要翻译： 公开了用于存储设备的低级格式的生产工具。 生产工具包括可连接的输入连接器和输出连接器，均符合接口标准。 输入连接器的至少一个冗余引脚与输出连接器的相应冗余引脚不连接，并且输出连接器的冗余引脚电连接以接收所提供的预定信号，其中存在指示低级格式模式 。

公开(公告)号：US20100088458A1

公开(公告)日：2010-04-08

申请号：US12245093

申请日：2008-10-03

申请人： YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

发明人： YU MAO KAO ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/10

CPC分类号： G06F12/04 ,  G06F12/0246 ,  G06F2212/1016 ,  Y02D10/13

摘要： An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset.

摘要翻译： 存储器的操作方法包括以下步骤：计算顺序写入命令的偏移和非易失性存储器的块的开头; 将块移动偏移; 并且通过顺序写入命令直接将数据从主机写入除块的第一页和最后一页之外的页面。 在一个实施例中，页面是提供最佳写入效率的逻辑页面，并且在计算偏移量之前确定。 通过偏移移位块的步骤是通过偏移增加页面中的对应逻辑块地址（LBA）。

公开(公告)号：US20100030933A1

公开(公告)日：2010-02-04

申请号：US12183229

申请日：2008-07-31

申请人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

发明人： Chih Wei Tsai ,  Chuang Cheng ,  Yung Li Ji ,  Shih Chieh Tai ,  Chih Cheng Tu ,  Fuja Shone

IPC分类号： G06F13/12 ,  G06F12/02

CPC分类号： G06F13/4239 ,  Y02D10/14 ,  Y02D10/151

摘要： A non-volatile memory storage device has a non-volatile memory, e.g., a flash memory, and a controller coupled to the non-volatile memory. The controller comprises a plurality of control circuits and an arbitration circuit. Each control circuit is configured to generate a request to update the chip-enable (CE) signals for non-volatile memory, and the arbitration circuit is configured to determine when the requests are acknowledged. The arbitration circuit generates acknowledge signals to the control circuits when all of the requests of the control circuits have been received by the arbitration circuit. The CE signals for non-volatile memory are updated when requests are acknowledged.

摘要翻译： 非易失性存储器存储设备具有非易失性存储器，例如闪存，以及耦合到非易失性存储器的控制器。 控制器包括多个控制电路和仲裁电路。 每个控制电路被配置为产生用于更新用于非易失性存储器的芯片使能（CE）信号的请求，并且仲裁电路被配置为确定何时请求被确认。 当仲裁电路已经接收到控制电路的所有请求时，仲裁电路向控制电路产生确认信号。 当请求被确认时，更新用于非易失性存储器的CE信号。

公开(公告)号：US20090259819A1

公开(公告)日：2009-10-15

申请号：US12100136

申请日：2008-04-09

申请人： YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

发明人： YEN MING CHEN ,  SHIH CHIEH TAI ,  YUNG LI JI ,  CHIH NAN YEN ,  FUJA SHONE

IPC分类号： G06F12/02 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F13/4239

摘要： A method of wear leveling for a non-volatile memory is performed as follows. First, the non-volatile memory is divided into a plurality of zones including at least a first zone and a second zone. The first zone is written and/or erased in which one or more logical blocks have higher writing hit rate, and therefore the corresponding physical blocks in the first zone will be written more often. The next step is to find one or more free physical blocks in second zone. The physical blocks of the first zone are replaced by the physical blocks of the second zone if the number of write and/or erase to the first zone exceeds a threshold number. The replacement of physical blocks in the first zone by the physical blocks in the second zone may include the steps of copying data from the physical blocks in the first zone to the physical block in the second zone, and changing the pointer of logical blocks to point to the physical blocks in the second zone.

摘要翻译： 如下执行用于非易失性存储器的磨损均衡的方法。 首先，非易失性存储器被分成包括至少第一区域和第二区域的多个区域。 写入和/或擦除第一区域，其中一个或多个逻辑块具有较高的写入命中率，因此第一区域中相应的物理块将被更频繁地写入。 下一步是在第二个区域中找到一个或多个空闲的物理块。 如果第一区的写入次数和/或擦除次数超过阈值，则第一区的物理块被第二区的物理块替换。 通过第二区域中的物理块来替换第一区域中的物理块可以包括以下步骤：将数据从第一区域中的物理块复制到第二区域中的物理块，并将逻辑块的指针改变为点 到第二区的物理块。

公开(公告)号：US20090106472A1

公开(公告)日：2009-04-23

申请号：US12073283

申请日：2008-03-04

申请人： Yung-Li Ji ,  Chin-Nan Yen ,  Fu-Ja Shone

发明人： Yung-Li Ji ,  Chin-Nan Yen ,  Fu-Ja Shone

IPC分类号： G06F13/14

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： A virtual SATA port multiplier and a virtual SATA device are provided for a SATA system. The virtual SATA port multiplier uses a SATA physical layer for data transfer between it and a SATA host, and a non-physical layer for direct data transfer between it and the virtual SATA device. Since the data transfer between the virtual SATA port multiplier and the virtual SATA device is not carried out by way of SATA physical layers, no physical layer circuits are required accordingly, thereby reducing the manufacturing cost, power consumption and hardware size of the SATA system.

摘要翻译： 为SATA系统提供虚拟SATA端口倍增器和虚拟SATA设备。 虚拟SATA端口倍增器使用SATA物理层在其与SATA主机之间进行数据传输，以及用于在其与虚拟SATA设备之间进行直接数据传输的非物理层。 由于虚拟SATA端口倍增器与虚拟SATA设备之间的数据传输不是通过SATA物理层进行的，因此不需要物理层电路，从而降低了SATA系统的制造成本，功耗和硬件尺寸。

公开(公告)号：US07911840B2

公开(公告)日：2011-03-22

申请号：US12318872

申请日：2009-01-12

申请人： Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

发明人： Hsin-Hsien Wu ,  Yu-Mao Kao ,  Yung-Li Ji ,  Chih-Nan Yen ,  Fu-Ja Shone

IPC分类号： G11C14/00

CPC分类号： G11C16/349

摘要： A flash memory system includes a path selector to determine to write to a non-volatile memory, a volatile memory or both the non-volatile memory and the volatile memory when the flash memory system is to write data. A record is stored in the non-volatile memory which is updated the status of the non-volatile memory after each one or more writing operations. When the flash memory system is powered on after a power loss, it could be recovered to a command executed prior to the power loss or to any checkpoint prior to the power loss by using the record.

摘要翻译： 闪速存储器系统包括路径选择器，用于在闪存系统要写入数据时确定写入非易失性存储器，易失性存储器或非易失性存储器和易失性存储器。 一个记录被存储在非易失性存储器中，在每个一个或多个写入操作之后更新非易失性存储器的状态。 当闪存系统在掉电后上电时，可以将其恢复到在掉电前执行的命令，或者通过使用该记录恢复到断电前的任何检查点。

公开(公告)号：US20090198944A1

公开(公告)日：2009-08-06

申请号：US12026375

申请日：2008-02-05

申请人： FUJA SHONE ,  CHIH NAN YEN ,  YUNG LI JI

发明人： FUJA SHONE ,  CHIH NAN YEN ,  YUNG LI JI

IPC分类号： G06F12/02

CPC分类号： G06F13/409

摘要： An adaptive semiconductor memory device is used for being inserted into a host for storage. The semiconductor memory device comprises a non-volatile memory and a switch. The switch can be a logical switch or a physical switch that controls the semiconductor memory device to be in compliance with either a first specification version or a second specification version of the semiconductor memory device. The second specification version in comparison with the first specification version is used for higher capacity applications.

摘要翻译： 自适应半导体存储器件被用于插入主机以进行存储。 半导体存储器件包括非易失性存储器和开关。 开关可以是控制半导体存储器件符合半导体存储器件的第一规范版本或第二规范版本的逻辑开关或物理开关。 与第一个规范版本相比，第二个规范版本用于更高容量的应用。

公开(公告)号：US20090198919A1

公开(公告)日：2009-08-06

申请号：US12024149

申请日：2008-02-01

申请人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

发明人： Yung-Li Ji ,  Shih Chieh Tai ,  Chih Nan Yen ,  Fu-Ja Shone

IPC分类号： G06F12/00

CPC分类号： G06F3/0634 ,  G06F1/3221 ,  G06F1/3268 ,  G06F3/0625 ,  G06F3/0679 ,  Y02D10/154 ,  Y02D50/20

摘要： A non-volatile memory device, and a method for accessing the non-volatile memory device are provided. The non-volatile memory device is connected to a host via a bus. The non-volatile memory device comprises an MCU. By independently processing the particular commands using only the auxiliary circuit, the MCU can cease to operate, thus saving power. By setting the bus into power saving mode when the non-volatile memory device is busy, the host and the non-volatile memory device would not communicate mutually, thus, saving power.

摘要翻译： 提供非易失性存储器件，以及用于访问非易失性存储器件的方法。 非易失性存储器件通过总线连接到主机。 非易失性存储器件包括MCU。 通过仅使用辅助电路独立处理特定命令，MCU可以停止工作，从而节省电力。 通过在非易失性存储器件忙时将总线设置为省电模式，主机和非易失性存储器件将不会相互通信，从而节省电力。