公开(公告)号：US20210167737A1

公开(公告)日：2021-06-03

申请号：US17172676

申请日：2021-02-10

Applicant: STMicroelectronics S. r. I.

Inventor： Mattia Fausto Moretti ,  Paolo Pulici ,  Alessio Facen

IPC: H03F1/26 ,  H03F3/45

Abstract: A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

公开(公告)号：US20140095932A1

公开(公告)日：2014-04-03

申请号：US14038501

申请日：2013-09-26

Applicant: STMicroelectronics S. r. I. ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Daniele Mangano ,  Ignazio Antonino Urzi

IPC: G06F11/27

CPC classification number: G06F11/27 ,  G06F11/2236 ,  G06F11/3648

Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.

Abstract translation: 系统包括处理器和通过互连网络连接的多个电路，其中与每个电路相关联的是相应的通信接口，被配置为在相应电路和互连网络之间交换数据。 特别地，调试单元与每个通信接口相关联。 每个调试单元可配置为数据插入点，其中调试单元通过相应的通信接口将数据发送到互连网络，或者每个调试单元可配置为数据接收点，其中调试单元通过 来自互连网络的相应通信接口的装置。

公开(公告)号：US20030214856A1

公开(公告)日：2003-11-20

申请号：US10372639

申请日：2003-02-20

Applicant: STMicroelectronics S. r. I. ,  OVONYX Inc.

Inventor： Fabio Pellizzer ,  Agostino Pirovano

IPC: G11C007/00

CPC classification number: G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

Abstract: The phase change memory cell is formed by a resistive element and by a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction which is transverse to said first direction. The first and second thin portions are in direct electrical contact and define a contact area having sublithographic extent. The second thin portion is formed in a slit of sublithographic dimensions. According to a first solution, oxide spacer portions are formed in a lithographic opening, delimited by a mold layer. According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

Abstract translation: 相变存储单元由电阻元件和相变材料的存储区形成。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区具有第二薄部，所述第二薄部在与所述第一方向横切的第二方向上具有第二亚光刻尺寸。 第一和第二薄部分是直接电接触并限定具有亚光刻范围的接触区域。 第二薄部分形成在亚光刻尺寸的狭缝中。 根据第一种解决方案，氧化物间隔物部分形成在由模具层限定的光刻开口中。 根据不同的解决方案，牺牲区域形成在模具层的顶部上，并用于在模具层中形成亚光刻缝。