公开(公告)号：US08473675B2

公开(公告)日：2013-06-25

申请号：US12805098

申请日：2010-07-12

申请人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

发明人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/7203 ,  Y02D10/13

摘要： A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.

摘要翻译： 存储器系统包括用作目标设备的主存储器的第一存储器，具有低于第一存储器存取速度的访问速度的第二存储器，将第一存储器的预定区域固定为临时存储器的固定部件 第二存储器的存储区域和接收将数据写入第二存储器的指令的存储器控​​制部分将数据临时存储到第一存储器中，并将存储的数据从第一存储器传送到第二存储器。

公开(公告)号：US08423842B2

公开(公告)日：2013-04-16

申请号：US12782332

申请日：2010-05-18

申请人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

发明人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/50012 ,  G11C29/50016 ,  G11C29/56 ,  G11C2029/5002 ,  G11C2029/5004

摘要： A test apparatus for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.

摘要翻译： 一种用于测试包括存储单元的存储器件的测试装置。 测试装置包括存储器和控制器。 存储器存储第一个值。 控制器在给定的定时执行基于存储器单元的输出来确定作为阈值极限值来正确读取存储器单元的数据的第二值，计算第一值和第二值之间的差值， 基于第一值和第二值之间的差异输出劣化信息，并将存储在存储器中的第一值更新为第二值。

公开(公告)号：US20110010508A1

公开(公告)日：2011-01-13

申请号：US12805098

申请日：2010-07-12

申请人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

发明人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/7203 ,  Y02D10/13

摘要： A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.

摘要翻译： 存储器系统包括用作目标设备的主存储器的第一存储器，具有低于第一存储器存取速度的访问速度的第二存储器，将第一存储器的预定区域固定为临时存储器的固定部件 第二存储器的存储区域和接收将数据写入第二存储器的指令的存储器控​​制部分将数据临时存储到第一存储器中，并将存储的数据从第一存储器传送到第二存储器。

公开(公告)号：US4101658A

公开(公告)日：1978-07-18

申请号：US583696

申请日：1975-06-04

申请人： Mitsuru Yoshioka ,  Yuji Sendo ,  Koji Ishikura ,  Masayuki Murakami ,  Sadao Miyazaki

发明人： Mitsuru Yoshioka ,  Yuji Sendo ,  Koji Ishikura ,  Masayuki Murakami ,  Sadao Miyazaki

IPC分类号： A61K31/545 ,  C07D501/20

CPC分类号： C07D501/20 ,  Y02P20/55

摘要： Antibacterial cephalosporins of the following formula: ##STR1## WHEREIN A and B each is a hydrogen or an amino protecting group; X is a hydroxy or a carboxy protecting group; Y is a hydrogen, halogen, alkyl, alkoxy, or an alkylthio; R is a hydrogen or an alkyl; Z is a group of the formula ##STR2## (in which R.sup.1 and R.sup.2 are the same or different and are a hydrogen, optionally substituted hydrocarbon group, organic acyl, or a group of the formula ##STR3## respectively, in which M and M' are the same or different and are an oxygen or sulfur; R.sup.3 is a hydrocarbon group; R.sup.1 and R.sup.2 can be combined together directly or through a hetero atom); m is 0 or 1; and the broken line shows the presence of a double bond at position 2 or 3, preparable from the compounds shown by the above formula in which Z is an oxygen by treatment with a compound shown by the formula H.sub.2 Z; and pharmaceuticals containing these compounds.

摘要翻译： 抗细菌头孢菌素如下：其中A和B各自为氢或氨基保护基; X是羟基或羧基保护基; Y是氢，卤素，烷基，烷氧基或烷硫基; R是氢或烷基; Z是式（IMA）（其中R 1和R 2相同或不同，分别为氢，任选取代的烃基，有机酰基或式“IMAGE”的基团）的基团，其中M和M “相同或不同，为氧或硫; R3为烃基; R1和R2可以直接或通过杂原子组合在一起; m为0或1; 虚线表示在上述式表示的化合物2或3中存在双键，其中Z为氧，通过用式H2Z表示的化合物处理; 和含有这些化合物的药物。

公开(公告)号：US4035044A

公开(公告)日：1977-07-12

申请号：US696933

申请日：1976-06-17

申请人： Sadao Miyazaki

发明人： Sadao Miyazaki

IPC分类号： F16C23/10 ,  F16C33/30

CPC分类号： F16C23/10

摘要： A bearing assembly comprising a plurality of outer and inner rings individually having eccentric outer and inner circumferential axes. The rings are disposed successively one inside the other in a manner such that an inner ring slidably rotatably contacts about its outer circumference the inner circumference of its immediately outer ring, and are relatively rotated to easily adjust to bring the axis position of a shaft to be rotatably supported by the bearing precisely to a predetermined reference position. Means is also disclosed, which releasably holds the rings against rotation after the axis position of the shaft is fixed.

摘要翻译： 一种轴承组件，其包括多个外圈和内圈，其具有偏心的外周轴和内周轴。 这些环以相对于其外圈的内周的外周可滑动地可旋转地接触的内环，相对旋转容易地调整以使轴的轴位置为 由轴承可旋转地支撑精确地到预定的基准位置。 还公开了在轴的轴位置固定之后可释放地保持环抵抗旋转的装置。

公开(公告)号：US08738976B2

公开(公告)日：2014-05-27

申请号：US13163606

申请日：2011-06-17

申请人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

发明人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C5/00 ,  G11C5/04 ,  G11C29/56 ,  G11C2029/4002

摘要： A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison.

摘要翻译： 一种用于检测对象存储器的错误的存储器错误检测装置，所述存储器错误检测装置包括连接到所述对象存储器的存储器总线，连接到所述存储器总线的镜像存储器，以便接收与要写入的数据相同的数据 从所述主体存储器读取所接收的数据被写入所述镜像存储器，地址获取部分，被配置为获取与写入所述对象存储器的数据相关的地址;镜像存储器控制器，被配置为控制数据写入或读取; 基于所获取的地址的镜像存储器，比较器，被配置为比较从所述对象存储器读取的数据和从所述镜像存储器读取的数据;以及错误检测器，被配置为基于所述比较的结果来检测数据错误。

公开(公告)号：US08495463B2

公开(公告)日：2013-07-23

申请号：US12725893

申请日：2010-03-17

申请人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

发明人： Sadao Miyazaki ,  Osamu Ishibashi ,  Rikizo Nakano

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/1208

摘要： A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.

摘要翻译： 提供存储器控制装置。 存储器控制装置被配置为控制对包括多个存储区域的存储装置的访问。 存储器控制装置包括：缺陷检测单元，被配置为检测可能不存储数据的存储区域的缺陷区域。 存储器控制装置还包括：存储处理单元，被配置为将包括使用缺陷检测单元检测到的缺陷区域的地址信息的缺陷信息存储到存储区域中。 数据写入单元也包括在存储器控制装置中。 数据写入单元被配置为基于使用存储处理单元存储的缺陷信息将已写入缺陷区域的数据写入除了包括缺陷区域的存储区域之外的存储区域中。

公开(公告)号：US20120254663A1

公开(公告)日：2012-10-04

申请号：US13430766

申请日：2012-03-27

申请人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

发明人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

IPC分类号： G06F11/263

CPC分类号： G11C29/50012 ,  G01R31/3187 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/08 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/14 ,  H04L25/0278

摘要： A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.

摘要翻译： 公开了一种半导体存储器件，其包括被配置为连接到在存储器块和输入 - 输出端子之间传输数据信号或数据选通信号的总线的ODT电路; 第一开关，被配置为插入到所述存储器块和所述ODT电路之间的总线中; 模式控制器，被配置为在所述存储器块的测试期间关闭所述第一开关; 以及配置为连接到ODT电路的振荡器，其中在存储器块的测试期间将测试信号从振荡器提供给ODT电路。

公开(公告)号：US20100251041A1

公开(公告)日：2010-09-30

申请号：US12725893

申请日：2010-03-17

申请人： Sadao MIYAZAKI ,  Osamu ISHIBASHI ,  Rikizo NAKANO

发明人： Sadao MIYAZAKI ,  Osamu ISHIBASHI ,  Rikizo NAKANO

IPC分类号： G06F12/02 ,  G11C29/08 ,  G06F11/26

CPC分类号： G11C29/44 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/1208

摘要： A memory control device is provided. The memory control device is configured to control access to a storage device including a plurality of storage areas. The memory control device includes a defect detecting unit configured to detect a defective area of a storage area into which data may not be stored. The memory control device also includes a storage processing unit configured to store defect information including address information of the defective area detected using the defect detecting unit into a memory area. A data writing unit is also included in the memory control device. The data writing unit is configured to write data, which has been written into the defective area, into a storage area other than the storage area comprising the defective area based on the defect information stored using the storage processing unit.

摘要翻译： 提供存储器控制装置。 存储器控制装置被配置为控制对包括多个存储区域的存储装置的访问。 存储器控制装置包括：缺陷检测单元，被配置为检测可能不存储数据的存储区域的缺陷区域。 存储器控制装置还包括：存储处理单元，被配置为将包括使用缺陷检测单元检测到的缺陷区域的地址信息的缺陷信息存储到存储区域中。 数据写入单元也包括在存储器控制装置中。 数据写入单元被配置为基于使用存储处理单元存储的缺陷信息将已写入缺陷区域的数据写入除了包括缺陷区域的存储区域之外的存储区域中。

公开(公告)号：US08868990B2

公开(公告)日：2014-10-21

申请号：US13430766

申请日：2012-03-27

申请人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

发明人： Rikizo Nakano ,  Osamu Ishibashi ,  Sadao Miyazaki

IPC分类号： G11C29/00 ,  G06F13/00 ,  H03K19/003 ,  H03K19/094 ,  G11C29/50 ,  G11C29/02 ,  G11C29/04 ,  G01R31/3187 ,  G11C29/12 ,  G11C29/08 ,  G11C29/14 ,  H04L25/02

CPC分类号： G11C29/50012 ,  G01R31/3187 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/08 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/14 ,  H04L25/0278

摘要： A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.

摘要翻译： 公开了一种半导体存储器件，其包括被配置为连接到在存储器块和输入 - 输出端子之间传输数据信号或数据选通信号的总线的ODT电路; 第一开关，被配置为插入到所述存储器块和所述ODT电路之间的总线中; 模式控制器，被配置为在所述存储器块的测试期间关闭所述第一开关; 以及配置为连接到ODT电路的振荡器，其中在存储器块的测试期间将测试信号从振荡器提供给ODT电路。