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公开(公告)号：US09477610B2
公开(公告)日：2016-10-25
申请号：US13995381
申请日：2011-12-23
CPC分类号： G06F12/0891 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/126 , G06F12/128 , G06F2212/621 , G06F2212/65 , G06F2212/683
摘要： Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.
摘要翻译： 有效管理缓存中的数据的方法和设备。 高速缓存中的数据可以基于分配给数据的优先级来管理。 数据可以由使用数据的虚拟地址的进程请求。 请求的数据可以被称为地址范围优先级分配器（ARP）的计算机系统中的组件分配优先级。 如果请求的数据的虚拟地址在虚拟地址的特定范围内，则ARP可以向所请求的数据分配特定优先级。 分配的特定优先级可以是高优先级，并且虚拟地址的特定范围可以小于高速缓存的容量。
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公开(公告)号：US10102124B2
公开(公告)日：2018-10-16
申请号：US13993716
申请日：2011-12-28
IPC分类号： G06F13/00 , G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.
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公开(公告)号：US08533422B2
公开(公告)日：2013-09-10
申请号：US12895387
申请日：2010-09-30
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译： 一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。 下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。 预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。 每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。 高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。 高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。
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公开(公告)号：US09201792B2
公开(公告)日：2015-12-01
申请号：US13996012
申请日：2011-12-29
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译： 多核处理装置可以提供高速缓存探针和数据检索方法。 该方法可以包括将请求者的存储器请求发送到记录保存结构。 存储器请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。 本地最后一个访问者可能在请求者所属的本地域内。 该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。
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公开(公告)号：US20140201446A1
公开(公告)日：2014-07-17
申请号：US13993716
申请日：2011-12-28
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F13/28
摘要： A micro-architecture may provide a hardware and software of a high bandwidth write command. The micro-architecture may invoke a method to perform the high bandwidth write command. The method may comprise sending a write request from a requester to a record keeping structure. The write request may have a memory address of a memory that stores requested data. The method may further determine copies of the requested data being present in a distributed cache system outside the memory, sending invalidation requests to elements holding copies of the requested data in the distributed cache system, sending a notification to the requester to inform presence of copies of the requested data and sending a write response message after a latest value of the requested data and all invalidation acknowledgements have been received.
摘要翻译： 微架构可以提供高带宽写命令的硬件和软件。 微架构可以调用执行高带宽写入命令的方法。 该方法可以包括从请求者向记录保存结构发送写入请求。 写请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以确定存储在存储器外部的分布式高速缓存系统中的所请求数据的副本，向分发的高速缓存系统发送无效请求给保存所请求数据的副本的元件，向请求者发送通知，以通知存在副本 所请求的数据和在所请求的数据的最新值和所有无效确认已经被接收之后发送写入响应消息。
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公开(公告)号：US20130339621A1
公开(公告)日：2013-12-19
申请号：US13995381
申请日：2011-12-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/1009 , G06F12/1027 , G06F12/1054 , G06F12/126 , G06F12/128 , G06F2212/621 , G06F2212/65 , G06F2212/683
摘要： Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity.
摘要翻译： 有效管理缓存中的数据的方法和设备。 高速缓存中的数据可以基于分配给数据的优先级来管理。 数据可以由使用数据的虚拟地址的进程请求。 请求的数据可以被称为地址范围优先级分配器（ARP）的计算机系统中的组件分配优先级。 如果请求的数据的虚拟地址在虚拟地址的特定范围内，则ARP可以向所请求的数据分配特定优先级。 分配的特定优先级可以是高优先级，并且虚拟地址的特定范围可以小于高速缓存的容量。
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公开(公告)号：US20130326147A1
公开(公告)日：2013-12-05
申请号：US13996012
申请日：2011-12-29
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/082
摘要： A multi-core processing apparatus may provide a cache probe and data retrieval method. The method may comprise sending a memory request from a requester to a record keeping structure. The memory request may have a memory address of a memory that stores requested data. The method may further comprise determining that a local last accessor of the memory address may have a copy of the requested data up to date with the memory. The local last accessor may be within a local domain that the requester belongs to. The method may further comprise sending a cache probe to the local last accessor and retrieving a latest value of the requested data from the local last accessor to the requester.
摘要翻译： 多核处理装置可以提供高速缓存探针和数据检索方法。 该方法可以包括将请求者的存储器请求发送到记录保存结构。 存储器请求可以具有存储请求的数据的存储器的存储器地址。 该方法还可以包括确定存储器地址的本地最后访问器可以具有与存储器一起的所请求数据的副本。 本地最后一个访问者可能在请求者所属的本地域内。 该方法还可以包括向本地最后一个访问器发送高速缓存探测器，并且从本地最后一个访问器检索所请求的数据的最新值到请求者。
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公开(公告)号：US20120084497A1
公开(公告)日：2012-04-05
申请号：US12895387
申请日：2010-09-30
CPC分类号： G06F12/0862 , G06F9/3816 , G06F2212/452 , G06F2212/6024 , Y02D10/13
摘要： An apparatus of an aspect includes a prefetch cache line address predictor to receive a cache line address and to predict a next cache line address to be prefetched. The next cache line address may indicate a cache line having at least 64-bytes of instructions. The prefetch cache line address predictor may have a cache line target history storage to store a cache line target history for each of multiple most recent corresponding cache lines. Each cache line target history may indicate whether the corresponding cache line had a sequential cache line target or a non-sequential cache line target. The cache line address predictor may also have a cache line target history predictor. The cache line target history predictor may predict whether the next cache line address is a sequential cache line address or a non-sequential cache line address, based on the cache line target history for the most recent cache lines.
摘要翻译： 一方面的装置包括预取高速缓存行地址预测器，用于接收高速缓存行地址并预测要预取的下一个高速缓存行地址。 下一个高速缓存行地址可以指示具有至少64字节指令的高速缓存行。 预取高速缓存线地址预测器可以具有高速缓存行目标历史存储器，以存储多个最新对应的高速缓存行中的每一个的高速缓存行目标历史。 每个高速缓存行目标历史可以指示对应的高速缓存线是否具有顺序高速缓存行目标或非顺序高速缓存行目标。 高速缓存行地址预测器也可以具有高速缓存行目标历史预测器。 高速缓存行目标历史预测器可以基于最近的高速缓存行的高速缓存行目标历史来预测下一个高速缓存行地址是顺序高速缓存行地址还是非顺序高速缓存行地址。
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