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23 条记录 (耗时 0.028 秒)

    Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof
    5.
    发明授权
    Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof 有权
    带蚀刻停止层的位线接头上的位线着陆焊盘和无边界触点及其制造方法

    公开(公告)号：US06350649B1

    公开(公告)日：2002-02-26

    申请号：US09699849

    申请日：2000-10-30

    申请人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

    发明人： Hong-Sik Jeong ,  Won-Suk Yang ,  Ki-Nam Kim

    IPC分类号： H01L218242

    CPC分类号： H01L27/10894 ,  H01L27/10855

    摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer to be coupled to the underlying stud. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

    摘要翻译： 在多层电路的层之间选择性地设置蚀刻停止层，以便在随后的制造过程中允许杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在要连接到下面的螺柱的上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

    Semiconductor memory device and method for manufacturing the same
    6.
    发明申请
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US20050167717A1

    公开(公告)日：2005-08-04

    申请号：US11080032

    申请日：2005-03-14

    申请人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    发明人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

    摘要翻译： 导电部分将形成在第一层间绝缘层中的半导体衬底上形成的下导电层连接到形成在下导电层上的上导电层，并设置在第二层间绝缘层中。 该部分被分成至少一个插头和垫。 在第一层间绝缘层和第二层间绝缘层的下部形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得形成在第二层间绝缘层的分割部分中的分隔插塞的上下宽度彼此不是很大的不同。 形成在第二层间绝缘层的上部的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会通过焊盘不期望地连接到相邻的上部导电层。

    Semiconductor memory device and method for manufacturing the same
    7.
    发明授权
    Semiconductor memory device and method for manufacturing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：US07462523B2

    公开(公告)日：2008-12-09

    申请号：US11080032

    申请日：2005-03-14

    申请人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    发明人： Won-Suk Yang ,  Sang-Hoo Song ,  Ki-Nam Kim ,  Hong-Sik Jeong

    IPC分类号： H01L29/72

    CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/10882 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conductive portion connects a lower conductive layer formed on a semiconductor substrate provided in a first interlayer insulating layer to an upper conductive layer formed on the lower conductive layer, and provided in a second interlayer insulating layer. This portion is divided into at least one plug and a pad. At least one plug is formed in a first interlayer insulating layer and the lower part of a second interlayer insulating layer. The second interlayer insulating layer is divided into a plurality of interlayer insulating layers so that upper and lower widths of the divided plugs formed in the divided portion of the second interlayer insulating layer are not greatly different from each other. The pad formed on the upper portion of the second interlayer insulating layer has an upper width such that the upper conductive layer connected to the pad is not undesirably connected to an adjacent upper conductive layer via the pad.

    摘要翻译： 导电部分将形成在第一层间绝缘层中的半导体衬底上形成的下导电层连接到形成在下导电层上的上导电层，并设置在第二层间绝缘层中。 该部分被分成至少一个插头和垫。 在第一层间绝缘层和第二层间绝缘层的下部形成至少一个插塞。 第二层间绝缘层被分成多个层间绝缘层，使得形成在第二层间绝缘层的分割部分中的分隔插塞的上下宽度彼此不是很大的不同。 形成在第二层间绝缘层的上部的焊盘具有上部宽度，使得连接到焊盘的上部导电层不会通过焊盘不期望地连接到相邻的上部导电层。

    Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region
    9.
    发明授权
    Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region 有权
    在周边区域中制造具有双重侧壁间隔物的MOS晶体管的方法和在单元区域中的单个侧壁间隔物

    公开(公告)号：US07888198B1

    公开(公告)日：2011-02-15

    申请号：US09313659

    申请日：1999-05-18

    申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

    发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

    IPC分类号： H01L21/00

    CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

    摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

    摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。

    Method for fabricating a semiconductor device having different gate oxide layers
    10.
    发明授权
    Method for fabricating a semiconductor device having different gate oxide layers 有权
    制造具有不同栅氧化层的半导体器件的方法

    公开(公告)号：US6136657A

    公开(公告)日：2000-10-24

    申请号：US315341

    申请日：1999-05-20

    申请人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

    发明人： Won-Suk Yang ,  Chang-Hyun Cho ,  Ki-Nam Kim

    IPC分类号： H01L27/108 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L29/423 ,  H01L21/336 ,  H01L21/31

    CPC分类号： H01L29/42368 ,  H01L21/28167 ,  H01L21/823462 ,  H01L21/28211 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S438/981

    摘要： A method for fabricating a semiconductor device with different gate oxide layers is provided. In this method, oxidation is controlled in accordance with the active area dimension so that the oxide grows more thinly at a wider active width in a peripheral region, and grows more thickly at a narrower active width in a cell array region. In this method, a gate pattern is formed over a semiconductor substrate having different active areas. Gate spacer are formed and an active-dimension-dependant oxidation process is then performed to grow oxide layers of different thicknesses in the cell array region and the peripheral region.

    摘要翻译： 提供一种制造具有不同栅氧化层的半导体器件的方法。 在该方法中，根据有源面积尺寸控制氧化，使得氧化物在周边区域中以更宽的有源宽度更薄地生长，并且在单元阵列区域中以较窄的有源宽度生长更厚。 在该方法中，在具有不同有源区域的半导体衬底上形成栅极图案。 形成栅极间隔物，然后执行活性尺寸依赖性氧化工艺以在电池阵列区域和外围区域中生长不同厚度的氧化物层。