公开(公告)号：US08174681B2

公开(公告)日：2012-05-08

申请号：US12349223

申请日：2009-01-06

申请人： Ioana Graur ,  Geng Han ,  Scott M. Mansfield ,  Michael Scaman

发明人： Ioana Graur ,  Geng Han ,  Scott M. Mansfield ,  Michael Scaman

IPC分类号： G03B27/32 ,  G01D18/00

CPC分类号： G03F7/70441 ,  G03F7/705

摘要： A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.

摘要翻译： 提供了一种用于校准光刻工艺的模型的方法，该方法包括定义在集成电路布局中期望的光刻模型参数的参数空间。 参数空间根据距离模型参数的预定最小值和最大值的范围的光刻模型参数的二进制值定义。 二进制值可以在最大和最小参数值之间均匀递增，也可以根据权重分配。 光刻模型被校准为初始校准测试图案。 评估所得到的模拟校准模式以确定模型参数空间是否被充分填充。 如果参数空间超过或不足，校准模式将被修改，直到校准模式测试值充分填充参数空间，以便最终校准的光刻过程模型将在图像参数的全范围内更可靠地预测图像。

公开(公告)号：US08166423B2

公开(公告)日：2012-04-24

申请号：US12555219

申请日：2009-09-08

申请人： Scott M. Mansfield ,  James A. Bruce ,  Gregory J. Dick ,  Ioana Graur

发明人： Scott M. Mansfield ,  James A. Bruce ,  Gregory J. Dick ,  Ioana Graur

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.

摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。

公开(公告)号：US20110271238A1

公开(公告)日：2011-11-03

申请号：US12770791

申请日：2010-04-30

申请人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

发明人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F7/203 ,  G03F7/70466

摘要： Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

摘要翻译： 通过执行将公差带分解成多个掩模以在多次曝光处理中使用来提供防止合并形状的可能性的最终尺寸。 这允许开路和短路故障机制之间的最大过程纬度，同时还提供了一种在电路的关键区域中强制执行严格的CD容限的机制。 该分解能够与放置在每个掩模上的各种类型的形状以及用于打印每个掩模的源共同优化。 一旦公差带被分解到两个或更多个掩模上，就可采用标准的基于公差带的数据准备方法来产生最终的掩模形状。

公开(公告)号：US07765021B2

公开(公告)日：2010-07-27

申请号：US12015077

申请日：2008-01-16

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Mohamed Talbi

IPC分类号： G06F19/00 ,  G06F17/50 ,  G06K9/00

CPC分类号： G03F7/70508 ,  G03F1/36 ,  G03F1/68 ,  G03F7/705

摘要： A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

摘要翻译： 提供了一种用于执行该方法的方法和计算机程序产品和系统，用于设计在半导体集成电路的制造中使用的掩模，其中在掩模设计过程中使用光刻处理的模型。 更具体地，在晶片上的工艺模型是使用来自测试图案的测量校准的光学图像参数的函数。 对于给定的感兴趣评估点，计算由晶片上过程模型模拟的预测响应的不确定性度量，作为在给定评估点处模拟的总体光学图像参数与集体光学图像参数之间的距离度量的函数 校准数据点。 不确定性度量优选地也是晶片上工艺模型响应对光学图像参数变化的灵敏度的函数。

公开(公告)号：US20080127029A1

公开(公告)日：2008-05-29

申请号：US11554904

申请日：2006-10-31

申请人： Ioana Graur ,  Geng Han ,  Scott M. Mansfield ,  Lars W. Liebmann

发明人： Ioana Graur ,  Geng Han ,  Scott M. Mansfield ,  Lars W. Liebmann

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

摘要翻译： 提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。 在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。 然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。 掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

公开(公告)号：US07266798B2

公开(公告)日：2007-09-04

申请号：US11163264

申请日：2005-10-12

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Azalia Krasnoperova ,  Ioana Graur

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Azalia Krasnoperova ,  Ioana Graur

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.

摘要翻译： 通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。 该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束 特征对其他层的影响。 该方法可以在用于在计算机系统上执行的计算机程序产品中实现。 所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

公开(公告)号：US06421820B1

公开(公告)日：2002-07-16

申请号：US09460034

申请日：1999-12-13

申请人： Scott M. Mansfield ,  Lars W. Liebmann ,  Shahid Butt ,  Henning Haffner

发明人： Scott M. Mansfield ,  Lars W. Liebmann ,  Shahid Butt ,  Henning Haffner

IPC分类号： G06F1750

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： A semiconductor device can be fabricated using a photomask that has been modified using an assist feature design method (see e.g., FIG. 4A) based on normalized feature spacing. Before the device can be fabricated, a layout of original shapes is designed (402). For at least some of the original shapes, the width of the shape and a distance to at least one neighboring shape are measured (404). A modified shape can then be generated by moving edges of the original shape based on the width and distance measurements (406). This modification can be performed on some or all of the original shapes (408). For each of the modified shapes, a normalized space and correct number of assist features can be computed (410). The layout is then modified by adding the correct number of assist features in a space between the modified shape and the neighboring shape (412). This modified layout can then be used in producing a photomask, which can in turn be used to produce a semiconductor device.

摘要翻译： 可以使用已经基于归一化特征间隔使用辅助特征设计方法（参见例如图4A）修改的光掩模来制造半导体器件。 在可以制造设备之前，设计原始形状的布局（402）。 对于至少一些原始形状，测量形状的宽度和至少一个相邻形状的距离（404）。 然后可以通过基于宽度和距离测量来移动原始形状的边缘来生成修改的形状（406）。 可以对部分或全部原始形状执行该修改（408）。 对于每个修改的形状，可以计算归一化空间和正确数量的辅助特征（410）。 然后通过在修改的形状和相邻形状之间的空间中添加正确数量的辅助特征来修改布局（412）。 然后，该修改后的布局可用于制造光掩模，光掩模又可用于制造半导体器件。

公开(公告)号：US06413683B1

公开(公告)日：2002-07-02

申请号：US09602966

申请日：2000-06-23

申请人： Lars W. Liebmann ,  Scott M. Mansfield

发明人： Lars W. Liebmann ,  Scott M. Mansfield

IPC分类号： G03F900

CPC分类号： G03F1/36

摘要： A method for developing a photomask layout by which an electrical circuit is imaged that includes introducing sub resolution assist features into a photomask layout by (1) sorting selected details of the main electrical circuit undergoing enhancement according to a predetermined order of importance of enhancement of the selected details of the main electrical circuit to the overall performance of the main electrical circuit, (2) establishing a prioritization for sub resolution assist features associated with the selected details of the main electrical circuit based on the predetermined order of importance of the selected details of the main electrical circuit with which the sub resolution assist features are associated, and (3) incorporating sub resolution assist features in the photomask layout in accordance with the established prioritization of the sub resolution features.

摘要翻译： 一种用于开发光掩模布局的方法，通过该方法，电路被成像，其包括通过以下方式将子分辨率辅助特征引入到光掩模布局中：（1）根据预先确定的增强重要性顺序对经历增强的主电路的选定细节进行排序 选择主电路的细节到主电路的总体性能，（2）基于所选择的细节的预定重要性顺序，建立与主电路的选定细节相关联的子分辨率辅助特征的优先级 与子分辨率辅助特征相关联的主电路，以及（3）根据子分辨率特征的确定的优先级，在光掩模布局中并入子分辨率辅助特征。

公开(公告)号：US5004307A

公开(公告)日：1991-04-02

申请号：US508224

申请日：1990-04-12

申请人： Gordon S. Kino ,  Scott M. Mansfield

发明人： Gordon S. Kino ,  Scott M. Mansfield

IPC分类号： G01Q60/18 ,  G02B1/02 ,  G02B21/02 ,  G02B21/33

CPC分类号： G01Q60/22 ,  B82Y20/00 ,  B82Y35/00 ,  G02B1/02 ,  G02B21/02 ,  G02B21/33

摘要： An optical microscope which includes a high refractive index solid immersion lens interposed between the objective lens and the object being viewed to provide a microscope having resolution which is far better than the Rayleigh diffraction limit in air.

摘要翻译： 一种光学显微镜，其包括介于物镜和物体之间的高折射率固体浸没透镜，以提供具有远远优于空气中的瑞利衍射极限的分辨率的显微镜。

公开(公告)号：US08392871B2

公开(公告)日：2013-03-05

申请号：US12770791

申请日：2010-04-30

申请人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

发明人： Scott M. Mansfield ,  Geng Han ,  Ioana C. Graur

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70 ,  G03F7/203 ,  G03F7/70466

摘要： Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

摘要翻译： 通过执行将公差带分解成多个掩模以在多次曝光处理中使用来提供防止合并形状的可能性的最终尺寸。 这允许开路和短路故障机制之间的最大过程纬度，同时还提供了一种在电路的关键区域中强制执行严格的CD容限的机制。 该分解能够与放置在每个掩模上的各种类型的形状以及用于打印每个掩模的源共同优化。 一旦公差带被分解到两个或更多个掩模上，就可采用标准的基于公差带的数据准备方法来产生最终的掩模形状。