公开(公告)号：US5890197A

公开(公告)日：1999-03-30

申请号：US989789

申请日：1997-12-12

申请人： Shigeki Nagasaka

发明人： Shigeki Nagasaka

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/4096 ,  G06F12/00

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： A semiconductor memory device including a serial I/O buffer; DRAM cells; and SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the second portions arc transferred to the serial input output buffer. The semiconductor-memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating first and second signals. When the mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.

摘要翻译： 一种包括串行I / O缓冲器的半导体存储器件; DRAM单元; 并且SAM单元排成一行，SAM单元对应于一行中的DRAM单元。 在第一模式的装置中，SAM单元被划分为每个具有边界的N个第一部分，存储在SAM单元中的数据被顺序地传送到串行I / O缓冲器，直到第一部分的边界内的SAM单元被传送 到串行I / O缓冲区。 在第二模式中，SAM单元被分成具有边界的M（N> M）个第二部分，存储在SAM单元中的数据被顺序传送到串行I / O缓冲器，直到第二部分边界内的SAM单元 电弧转移到串行输入输出缓冲器。 半导体存储器件还包括用于检测从第一模式到第二模式以及从第二模式到第一模式的变化的电路。 半导体存储器件还包括用于产生第一和第二信号的电路。 当模式从第一模式改变到第二模式时，电路产生第一信号。 当模式从第二模式改变到第一模式时，电路产生第二信号。

公开(公告)号：US06853770B2

公开(公告)日：2005-02-08

申请号：US10250339

申请日：2001-12-25

申请人： Frank Xiaofan Zhu ,  Shigeki Nagasaka ,  Naoki Morimoto ,  Kenichi Nakama

发明人： Frank Xiaofan Zhu ,  Shigeki Nagasaka ,  Naoki Morimoto ,  Kenichi Nakama

IPC分类号： G02B6/42 ,  G02B5/18 ,  G02B6/34 ,  H01J14/02

CPC分类号： G02B6/4215 ,  G02B6/2931 ,  G02B6/3512 ,  G02B6/4225 ,  G02B6/4227

摘要： The present invention relates to a method of aligning and assembling an optical demultiplexer module having an input fiber, a collimator lens, a diffraction grating, and a photodetector array, and a mechanism for automatically aligning such an optical demultiplexer module. The method comprises the steps of preparing a submodule A including the input fiber and the photodetector array and a submodule B including the diffraction grating and the collimator lens, preparing an alignment jig for allowing the submodules A, B to move independently of each other, fixing the submodules A, B to the adjustment jig, and applying light from the input fiber and moving the submodule B with respect to the submodule A for maximizing a light output from a photodetector.

摘要翻译： 本发明涉及一种对准和组装具有输入光纤，准直透镜，衍射光栅和光电检测器阵列的光解复用器模块的方法，以及用于自动对准这种光解复用器模块的机构。 该方法包括以下步骤：制备包括输入光纤和光电检测器阵列的子模块A和包括衍射光栅和准直透镜的子模块B，准备对准夹具以使子模块A，B彼此独立地移动，固定 子模块A，B到调整夹具，并且从输入光纤施加光并使子模块B相对于子模块A移动，以使从光电检测器输出的光最大化。

公开(公告)号：US07139139B2

公开(公告)日：2006-11-21

申请号：US10359108

申请日：2003-02-05

申请人： Shigeki Nagasaka ,  Kenichi Nakama

发明人： Shigeki Nagasaka ,  Kenichi Nakama

IPC分类号： G02B27/00 ,  G02B5/00 ,  G02B7/00

CPC分类号： G02B6/29307 ,  G02B6/2931 ,  G02B6/2938 ,  G02B6/4214 ,  H04J14/02

摘要： An optical module includes a package, which accommodates an optical system. A package main body has an opening. A lid is attached to the main body to close the opening of the main body. The lid seals the package. An anti-deterioration agent for preventing deterioration of the optical system is located inside the package at a position out of a light path of the optical system. The anti-deterioration agent includes at least one of desiccant and deoxidant.

公开(公告)号：US06974264B2

公开(公告)日：2005-12-13

申请号：US10093060

申请日：2002-03-08

申请人： Kenichi Nakama ,  Tsuyoshi Yamane ,  Shigeki Nagasaka

发明人： Kenichi Nakama ,  Tsuyoshi Yamane ,  Shigeki Nagasaka

IPC分类号： G02B6/34 ,  G02B6/42 ,  G02B6/32 ,  G02B6/43

CPC分类号： G02B6/4249 ,  G02B6/278 ,  G02B6/2931 ,  G02B6/29398 ,  G02B6/4204 ,  G02B6/4213 ,  G02B6/4215 ,  G02B6/4219 ,  G02B6/4244 ,  G02B6/4253 ,  G02B6/426

摘要： In a small-sized optical module, opposite side surfaces of a collimator lens (2) and opposite side surfaces of a polarization compensating filter (5) are fixed to opposite side surfaces of a rectangular frame (4). Two open surfaces are provided in the rectangular frame (4), so that optical components can be finely adjusted easily, and a large number of small-sized optical components can be aligned and assembled accurately. Reinforcing members (6) are provided in the open surfaces of the rectangular frame (4) so that the shape of the rectangular frame (4) can be retained against external force. After a diffraction grating (3) is fixed to the reinforcing members (6), the reinforcing members (6) with the diffraction grating (3) are adjusted, aligned and fixed to the rectangular frame (4).

摘要翻译： 在小型光模块中，准直透镜（2）的相对侧面和偏振补偿滤光片（5）的相对侧面固定在矩形框架（4）的相对侧面上。 在矩形框架（4）中设有两个敞开的表面，从而可以容易地调整光学部件，并且可以精确对准和组装大量的小尺寸光学部件。 加强构件（6）设置在矩形框架（4）的开放表面中，使得矩形框架（4）的形状可以抵抗外力而保持。 在将衍射光栅（3）固定到加强构件（6）之后，将具有衍射光栅（3）的加强构件（6）调整并对齐并固定在矩形框架（4）上。

公开(公告)号：US5748201A

公开(公告)日：1998-05-05

申请号：US405497

申请日：1995-03-16

申请人： Shigeki Nagasaka

发明人： Shigeki Nagasaka

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/4096 ,  G06F12/06

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： A semiconductor memory device including a serial I/O buffer; DRAM cells; and SAM cells arranged in line, the SAM cells corresponding to the DRAM cells in one row. In the device in a first mode, the SAM cells are divided into N first portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the first portions are transferred to the serial I/O buffer. In a second mode, the SAM cells are divided into M (N>M) second portions each having boundaries, data stored in the SAM cells being transferred to the serial I/O buffer sequentially until the SAM cells in the boundaries of the second portions are transferred to the serial input output buffer. The semiconductor memory device further includes a circuit for detecting changes from the first mode to the second mode and from the second mode to the first mode. The semiconductor memory device further includes a circuit for generating first and second signals. When the mode is changed from the first mode to the second mode, the circuit generates the first signal. When the mode is changed from the second mode to the first mode the circuit generates the second signal.

摘要翻译： 一种包括串行I / O缓冲器的半导体存储器件; DRAM单元; 并且SAM单元排成一行，SAM单元对应于一行中的DRAM单元。 在第一模式的装置中，SAM单元被划分为每个具有边界的N个第一部分，存储在SAM单元中的数据被顺序地传送到串行I / O缓冲器，直到第一部分的边界内的SAM单元被传送 到串行I / O缓冲区。 在第二模式中，SAM单元被分成具有边界的M（N> M）个第二部分，存储在SAM单元中的数据被顺序传送到串行I / O缓冲器，直到第二部分边界内的SAM单元 被传送到串行输入输出缓冲器。 半导体存储器件还包括用于检测从第一模式到第二模式以及从第二模式到第一模式的变化的电路。 半导体存储器件还包括用于产生第一和第二信号的电路。 当模式从第一模式改变到第二模式时，电路产生第一信号。 当模式从第二模式改变到第一模式时，电路产生第二信号。